On design of multiple-valued sequential reversible circuits for nanotechnology based systems

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

ABSTRACTQuantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.

Multi-level (ML) quantum logic can potentially reduce the number of inputs/outputs or quantum cells in a quantum circuit which is a limitation in current quantum technology. In this paper we propose theorems about ML-quantum and reversible logic circuits. New efficient implementations for some basic controlled ML-quantum logic gates, such as three-qudit controlled NOT, Cycle, and Self Shift gates are proposed. We also propose lemmas about r-level quantum arrays and the number of required gates for an arbitrary n-qudit ML gate. An equivalent definition of quantum cost (QC) of binary quantum gates for ML-quantum gates is introduced and QC of controlled quantum gates is calculated.

The design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. A fault model, namely, the Missing-Gate Fault (MGF) model, has been found to be more suitable for modeling defects in quantum circuits as compared to the classical fault models used for testing conventional CMOS circuits. In this paper, we propose two design-for-testability techniques with universal test set to detect MGFs in a reversible circuit. In these techniques, an [Formula: see text] reversible circuit implemented with [Formula: see text]-CNOT gates is transformed to a testable design with addition of two extra inputs lines and some additional gates, which uses a universal test set of size [Formula: see text] to detect the MGFs. The proposed DFT techniques are compared with earlier works and it has been shown that these techniques outperform the earlier techniques with respect to quantum cost overhead and percentage detection of the different MGFs.

Background: Multiple-Valued Logic (MVL) is the non-binary-valued system, in which more than two levels of information content are available, i.e., L>2. In modern technologies, the dual level binary logic circuits have normally been used. However, these suffer from several significant issues such as the interconnection considerations including the parasitics, area and power dissipation. The MVL circuits have been proved to be consisting of reduced circuitry and increased efficiency in terms of higher utilization of the circuit resources through multiple levels of voltage. Innumerable algorithms have been developed for designing such MVL circuits. Extended form is one of the algebraic techniques used in designing these MVL circuits. Voltage mode design has also been employed for constructing various types of MVL circuits. Novelty: This paper proposes a novel MVLTRANS inverter, designed using conventional CMOS and pass transistor logic based MVLPTL inverter. Binary to MVL Converter/Encoder and MVL to binary Decoder/Converter are also presented in the paper. In addition to the proposed decoder circuit, a 4-bit novel MVL Binary decoder circuit is also proposed. Tools Used: All these circuits are designed, implemented and verified using Cadence® Virtuoso tools using 180 nm technology library.

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively.

Design of sequential circuits by quantum-dot cellular automata

The reversible logic synthesis is a multi-objective optimization problem with rigorous constraints such as prohibiting the feedback and fan-out, and the same number of inputs and outputs, so it is difficult to be solved by general synthesis methods. Moreover, the synthesis methods of reversible logic circuits are very different from that of existing irreversible logic circuits. To make improvements in the capability and effectiveness of reversible logic synthesis, this paper proposes an algorithm of reversible logic gate-level evolutionary synthesis using multi-objective adaptive discrete differential evolution based on Pareto optimal. The synthesis experiments are conducted for a set of benchmark reversible logic circuits which are widely used in the reversible logic synthesis tests. The experiment results show that the proposed synthesis algorithm can give attention to multiple synthesis objectives at the same time, and has the capability to automatically synthesize the better reversible logic circuits, which verifies the feasibility and effectiveness of the proposed synthesis algorithm.

Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising direction so that several methods for synthesis, verification, and testing of reversible circuits have already been proposed. However, also methods for debugging, i.e., to determine error candidates in case of a failed verification, are required to complete the design flow. Even if first approaches have already been proposed, debugging of reversible circuits still is in the beginning. In this paper, we present an alternative method to automatically debug reversible circuits. We thereby focus on missing control errors -- an established error model in the design of reversible circuits. A new notion of an error candidate is proposed that relies on the observation of a necessary condition for error locations in reversible circuits. Using this notion, a set of error candidates is obtained that differs from the error candidates returned by previous methods. Thus, combining the approaches enhances the overall debugging flow. Experimental results demonstrate that a higher accuracy is obtained in significantly shorter run-time.

Logic circuits in digital electronics can generally be classified two categories-combinational and sequential logic circuits.There are several software-based applications and hardware description languages to describe the structure and behavior of electronic circuits.Although it is an easy to construct a state transition table from the state transition diagram,creating an excitation table according to the memory element type in the sequential circuit design is a very laborious and time-consuming task.After the logic functions extracted from the state transition tables are obtained,logic design verification can be carried out by a conventional simulator.This will require time and persistence much like learning any other skill.Computer science degrees include courses focused mainly on programming languages.There’s a strong case to be made for use of skills acquired in programming courses to shorten the learning curve.Thus, this work has proposed a method for the implementation of the circuit only the state equations of the sequential circuit without dealing with excitation tables.This eliminates the process of constructing the circuit schematically, since it does not require flip-flop selection.In this method, since the state equations can be expressed through buttonbox,checkbox,textbox etc.which are the basic elements of the programming language,the behavior of the circuit can be observed in a very short time.

This paper introduces a broad concept of don't cares in reversible and quantum logic circuits. Don't cares are classified into three categories: inputs, outputs, and conditions. Some heuristic methods to use these don't cares, when an optimization algorithm such as genetic algorithm is used, are also presented. We show that, these methods decrease the quantum cost of the reversible or quantum logic circuit, as well as the design time of the resulting circuit. Some examples are also synthesized and optimized using the don't care concept and genetic algorithms.

This paper presents a new algorithm MP(multiple pass) to synthesize large reversible binary circuits without ancilla bits. The MMD algorithm requires to store a truth table (or a Reed-Muller -RM transform) as a 2^n vector for a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with existing algorithms. In addition, our unique multipass approach where the circuit is synthesized with various, yet specific, minterm orders yields optimal solution. The algorithm returns a description of the optimal circuit with respect to gate count or quantum cost. Although the synthesis process is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

A new design for XOR gate-based reversible double Feynman gate in nano-scale quantum-dots

Reversible logic is an emerging research area. Its ability to reduce the power dissipation has made these circuits lossless circuits. Irreversible circuits or classical circuits have energy dissipation is proportional to the number of bits lost during computation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. It has application in diverse fields such as low power CMOS design, optical information processing, cryptography, quantum computation and nanotechnology. This paper proposes a reversible design of Flip Flops, Counters and Universal shift register. Universal shift register is an important memory element of the sequential circuit family. In this paper we proposed efficient design of reversible universal shift register that is optimized in terms of quantum cost, delay, garbage outputs. Each module has been coded using Verilog then simulated using Modelsim and prototyped in Xilinx-Spartan 3.