Controller Architecture for Memory BIST Algorithms

The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.

Area Overhead and Power Analysis of March Algorithms for Memory BIST

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10–20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to non optimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products.

A built-in self-test (BIST) scheme which partitions the fixed (instead of movable) capacitance plates of a capacitive MEMS device is proposed. The BIST technique divides the fixed capacitance plate(s) at each side of the movable microstructure into three portions: one for electrostatic activation and the other two equal portions for capacitance sensing. Due to such partitioning, the BIST technique can be applied to surface-, bulk-micromachined MEMS devices and other technologies. Further, sensitivity and symmetry BIST methods based on this partitioning are also introduced. The combination of both BIST modes covers a larger defect set, thus a robust testing for the device can be expected. The BIST technique is verified by three typical capacitive MEMS devices. Simulation results show that the proposed technique is an effective BIST solution for various capacitive MEMS devices.

A new flexible, hierarchical and distributed power-constrained embedded memory built-in self-test (BIST) architecture for complex and heterogeneous systems-on-a-chip (SOCs) is presented. The proposed architecture consists of a shared technology-independent BIST controller, low area and low power memory BIST wrappers and serial interconnect between them for low routing-overhead. Due to its flexibility, in addition to reducing routing complexity and achieving high test concurrency under power constraints, the presented solution can simultaneously support multiple test algorithms for heterogeneous memories, as well as embed custom test algorithms required for new memory faults.

Integration of diagnostics with a memory built-in self-test (BIST) allowing both an effective and efficient manufacturing test as well as an effective diagnostic capability is detailed. Detection of failures within a memory are the primary objective of an embedded memory BIST. Inclusion of comprehensive diagnostics, to isolate faults incurred during the manufacturing or design process, are an extension to the memory BISI, further utilizing the existing circuitry and functionality. Detection and diagnosis of failures within an embedded memory can be realized throughout the entire manufacturing process.

With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.

Design for Testability (DFT) provides for economic benefits and reduction in costs for design, manufacturing and support of electronic systems. The amalgamation of increased benefits and net reduced costs is value enjoyed throughout the life cycle of the system. While a number of formulas have been developed over the years to justify DFT, a unifying methodology is needed that can be used to calculate the overall economic value of DFT. The methodology we use in this paper relates known input benefit and cost parameters and map their dependencies to higher level DFT benefits and costs. This method demonstrates the numerous ways DFT can improve a system's life cycle value. It can also be used to justify the costs of DFT, such as added engineering labor, additional parts, higher cost boundary scan and built-in self test (BIST) parts. Moreover, they help convince financially focused management that DFT is a worthwhile investment even though the expenditures are in the early part of the life cycle and the return on that investment may be years later. Proponents of DFT need the methodology we present here to back up their assertions that DFT is profitable. Using dependencies lends itself to programming and calculations of DFT value can be readily performed by spreadsheet programs.

This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5/spl times/2/sup n/ vectors to the modified circuit under test (CUT), and counting the number of 1's in the output response. The second method uses the same test pattern generator (TPG), but faults are detected by a self comparison technique without the need of storing a signature. Finally, we propose a new adaptive BIST technique, where the TPG is driven by the past outputs of the CUT itself In all the cases, the TPG is universal, i.e., if does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector, nor any fault dictionary, is required. These approaches provide simplicity, less testing time and test data, and compare favorably with earlier BIST designs for CMOS circuits.

To reduce the area and developing time of the Memory Built-in Self-Test (MBIST) circuit has been challenged in the market. An architecture that could test memories different in size by only one MBIST circuit is presented in this paper. It is achieved by adding a data processing module and an address processing module into the mature and ready-made MBIST architecture. Base on this architecture, a MBIST circuit for the memories embedded in a SoC chip is successfully designed.

We present a testable built-in self test(BIST) design for phase-lock loop(PLL). The design can measure the clock jitter for PLL with high precision and high accuracy due to better utilization of the test integration and test subtraction techniques. Although the BIST circuit is implemented by all digital standard cells to achieve better reliability, it can even be applied to measure the analog clock jitter. Besides, for some DfT (design for test) techniques inserted to make BIST itself testable, we discuss the trade-off among area, timing, number of test patterns and fault coverage in this paper.

Built-in self test (BIST) techniques are widely used in today's complex integrated circuits, since they employ on-chip test pattern generation and response verification. Arithmetic BIST techniques utilize modules that commonly exist in datapath modules (accumulators, counters etc.). In order to perform the test generation and response verification operations. In order to detect sequential faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed, requires two-pattern tests. In this paper a novel algorithm for the generation of two-pattern tests is presented. The presented algorithm utilizes modules included in datapath circuitry to generate two-pattern tests; its implementation in hardware compares favorably with techniques that have been presented in the open literature

This article discusses design for testability automation for the Silc silicon compiler under development at GTE Laboratories, Inc. Our modular design for testability uses both built-in self-test and scan-path techniques for Slic's full custom VLSI designs. A test controller coordinates the testing of the chip's modules. Testability evaluation is performed using controllability/observability methods, and using a method based on information theory. A testable-by-construction approach is followed in order to synthesize blocks of testable logic. A testability ?expert? manages testability knowledge during the synthesis process and makes the ultimate testability decisions.

An original BIST (built-in self-test) scheme is proposed to cover some shortcomings of self-checking circuits and to ensure all tests needed for integrated circuits. In the BIST scheme, self-checking techniques and built-in self-test techniques are combined in an original way and take advantage one from the other. This results in a unified BIST scheme (UBIST), allowing a high fault coverage for all tests needed for integrated circuits, e.g. offline test (design verification, manufacturing test, and maintenance test) and online concurrent error detection. >

In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the memory. When the fault cells need to be operated, spares rows/columns will be used instead of faulty cells using Built-in self-repair (BISR) logic. Repairing logic includes either row repair/column repair or a combination of both. In this paper, we propose two methods, one is on the memory built-in self-test (BIST) for checking the memory array circuit. In the second method, an optimized BISR is employed to repair the faulty memory cells based upon the Built-in redundancy analysis. In the BIST method, our proposed method injects the faults into memory by using two fault injection techniques called saboteurs and mutants with optimized test pattern logic. After the injection of the faults in the memory cell, the fault memory is repaired with the proposed counting threshold algorithm for the BISR scheme. Simulation and synthesis results are obtained using Mentor Graphics and Xilinx ISE Design Suite. From our obtained results it can be inferred that various performance measures like power, area, and timing details are reduced in the proposed methods when compared with the existing exhaustive methods. And this proves that the performance of the overall process is found to be enhanced. Thereby yield can also be enhanced with minimum time to market.