Economics modeling of multichip modules testing strategies

Design for Testability (DFT) provides for economic benefits and reduction in costs for design, manufacturing and support of electronic systems. The amalgamation of increased benefits and net reduced costs is value enjoyed throughout the life cycle of the system. While a number of formulas have been developed over the years to justify DFT, a unifying methodology is needed that can be used to calculate the overall economic value of DFT. The methodology we use in this paper relates known input benefit and cost parameters and map their dependencies to higher level DFT benefits and costs. This method demonstrates the numerous ways DFT can improve a system's life cycle value. It can also be used to justify the costs of DFT, such as added engineering labor, additional parts, higher cost boundary scan and built-in self test (BIST) parts. Moreover, they help convince financially focused management that DFT is a worthwhile investment even though the expenditures are in the early part of the life cycle and the return on that investment may be years later. Proponents of DFT need the methodology we present here to back up their assertions that DFT is profitable. Using dependencies lends itself to programming and calculations of DFT value can be readily performed by spreadsheet programs.

We present a testable built-in self test(BIST) design for phase-lock loop(PLL). The design can measure the clock jitter for PLL with high precision and high accuracy due to better utilization of the test integration and test subtraction techniques. Although the BIST circuit is implemented by all digital standard cells to achieve better reliability, it can even be applied to measure the analog clock jitter. Besides, for some DfT (design for test) techniques inserted to make BIST itself testable, we discuss the trade-off among area, timing, number of test patterns and fault coverage in this paper.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

In this tutorial test fundamentals are reviewed to introduce key concepts in design for test and built-in self-test. Design for test and built-in self-test are illustrated by their implementation in single-chip conversion of a PCB design and a floating point co-processor design, respectively. The savings in design effort when testability is part of the initial design is stressed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design for testability (DFT) help in simplifying the ‘manufacturing tests’ used to detect post fabrication manufacturing defects in an integrated circuits (IC). The embedded memory tests in an integrated circuits utilize Built In Self Test (BIST) strategy. In this paper we have shown BIST technique and several algorithms used in BIST to test embedded memory. Such memory BIST technique comprises of address generator, controller, comparator and memory. The work presents the three different algorithms for implementing controller used in the memory BIST. The modeling of the memory BIST controller is performed using Verilog HDL to verify correctness of these memory controllers which are then synthesized using RTL compiler utilizing TSMC 90 nm and ARM 7 nm technology library. The paper shows the comparisons of area, power and timing results obtained from RTL compiler for these controller.

A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM. >

The multiple scan chain has been used in DFT (design for test) architectures primarily to reduce test application time. Since power is an emerging problem, in this paper, we present a design technique for multiple scan chains in BIST (built-in self test) to reduce average power dissipation and test application time, while maintaining the fault coverage. First, we partition the scan chain into a set of smaller chains of similar lengths in such a way that the total number of scan transitions in the scan chain is minimized. Then, we use a novel scan re-ordering algorithm in each smaller chain to further reduce the transitions. Experiments on ISCAS'89 benchmarks show up to 46.2% (average 24.4%) power reduction using the proposed technique, compared to the scan partitions given in the RTL description. Unlike previous approaches, our solution is computationally efficient and test-set independent and thus, can be effectively applied to large BIST circuitry.

Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named three-phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test generator for VLSI BIST design. Previous approaches to the problem of test generation have optimized computational efficiency at the expense of the required hardware overhead, or vice versa. Our design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive test. Based on three-phase cluster partitioning, a design generator named BISTSYN has been developed and implemented to facilitate the BIST design. The input to the design generator is a circuit description at the gate level which is viewed as a netlist. BISTSYN provides the BIST mechanisms as the output. For those conventional circuits which are extremely unsuitable for pseudo-exhaustive test, BISTSYN employs a circuit partitioning tool, named Autonomous, to partition the combinational portion of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. We demonstrate the effectiveness of BISTSYN by applying the method to different examples and practical VLSI designs. The detailed comparisons of our benchmark simulation results against those that would be obtained by existing techniques are also presented. >

Products motivated by performance-driven and/or density-driven goals are utilizing Multi-Chip Module (MCM) technology. However, this technology still has several challenging problems that need to be resolved before it becomes a widely adopted solution. One of the critical problems is meeting the quality requirements of MCM manufacturing, and hence reaching acceptable MCM assembly yields. This can be achieved by adopting a testing strategy, that first guarantees the quality of incoming bare dies and expensive substrates prior to module assembly, then ensures the functionality and performance of the assembled MCMs, and finally helps isolating the defected parts prior to the rework process. This paper presents a testability strategy that can be implemented mainly by incorporating Built-in Self-Test (BIST) and Boundary-Scan during the chip design cycle. And based on which the paper demonstrates the testing and diagnosis procedures needed to meet the above duality target. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate or attachment technologies adopted to build the MCM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testing is an integral part of the production and operation of computer systems, whether they are implemented in WS I or in more traditional technologies. As digital systems become more complex, they are characterized by more internal circuitry per I/O line and larger internal state spaces. This makes testing complex systems as integrated units very difficult. The testing problem can be made more tractable by partitioning them into subsystems that can be tested separately. With very complex integrated systems, this partitioning requires either design for testability, built-in self test (BIST) techniques, or both, since otherwise the entire integrated system would have to be tested through its inputs and outputs as a monolithic unit.

In order to reduce the test cost, built-in self test (BIST) is widely used. One of the serious problems of BIST is that the compacted signature in BIST has very little information for fault diagnosis. Especially, it is difficult to determine which tests detect a fault. Therefore, it is important to develop an efficient fault diagnosis method by using incompletely identified pass/fail information. Where the incompletely identified pass/fail information means that a failing test block consists of at least one failing test and some passing tests, and all of the tests in passing test blocks are the passing test. In this paper, we propose a method to locate open faults by using incompletely identified pass/fail information. Experimental results for ISCAS'85 and ITC'99 benchmark circuits show that the number of candidate faults becomes less than 5 in many cases.

This paper presents a built-in self-test (BIST) design of a high-speed C-testable divider. The divider can be fully tested using 72 test patterns irrespective of the circuit size (C-testability). Its test patterns, expected outputs, and control signals can be represented by sets of labels using a graph labeling technique. Due to the simplicity of the repetitive label sets, test patterns can be easily generated inside chips and responses to test patterns need not to be stored. Thus, use of expensive test equipment is not necessary. Results show that, for the BIST design of a 64-bit C-testable divider, its hardware overhead is less than 5%.

This article addresses the issue of improving energy efficiency in the testing of system-on-chip (SoC) semiconductor systems, including heterogeneous computing cores and AI accelerators. An analysis of SoC architecture and existing Design for Testability (DFT) methodologies is presented, considering energy-saving techniques such as clock gating, power gating, and dynamic voltage and frequency scaling (DVFS). A literature review highlights the insufficient development of a comprehensive approach to reducing power consumption specifically during testing procedures. Practical examples, including Qualcomm Snapdragon, Apple A-Series, and Tesla FSD, demonstrate that integrating low-power techniques into DFT can significantly reduce energy consumption (by an average of 20–35%) without compromising test coverage quality. The proposed analysis confirms the effectiveness of combining traditional scan chains, built-in self-test (BIST), and boundary scan with power management mechanisms, contributing to reduced thermal loads and increased reliability of modern SoCs in mass production. The findings presented in this article will be of interest to leading researchers and practicing engineers in the fields of microelectronics, materials science, and energy optimization, aiming to integrate advanced testing methodologies with innovative energy-saving solutions to develop reliable, high-performance, and environmentally sustainable semiconductor systems.

Built-in self-test (BIST) is a key design-for-testability technique for digital systems in nanometre technologies. BIST design is usually quite intrusive. In fact, BIST-per-scan or BIST-per-clock schemes require the replacement of all circuit registers by modified flip-flops or registers with extra functionality, which may lead to unacceptable area overhead and, especially, performance degradation. However, for some applications, system performance cannot be compromised by BIST insertion. Moreover, many applications have multiple clock domains and need to be self-tested at speed, during product lifetime. The functional-oriented mask-based BIST is proposed as a minimum impact BIST design methodology. The proposed approach uses testability metrics and circuit functionality to iteratively obtain a BIST solution with the required fault coverage (FC). It can be implemented in multiple clock domain designs and lead to short BIST sessions and a limited impact on system performance. A real world case study, for which system performance is critical, is used to demonstrate that high FC values in a sequential circuit can be achieved, operating at-speed with multiple clock signals, with minimum performance degradation and with lower hardware overhead than the one obtained with a BIST-per-scan solution. The case study is a two-clock domain Sync core for the Synchronisation and Link Board of electromagnetic calorimeter and hadron calorimeter detectors of the CERN compact Muon solenoid experiment.

Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. However, when deciding to adopt this emerging technology as a mainstream design approach, designers must consider the cost of 3D integration. IC testing is a key factor that affects the final product cost, and it could be a major portion of the total IC cost. In 3D IC design, various testing strategies and different integration methods could affect the final product cost dramatically, and the interaction with other cost factors could result in various trade-offs. This paper develops a comprehensive and parameterized testing cost model for 3D IC integration, and analyzes the trade-offs associated with testing strategies and testing circuit overheads. With the proposed testing cost model, designers can explore the most cost-effective integration and testing strategies for 3D IC chips.