Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis

The rise of three-dimensional (3D) IC layouts necessitates the development of unique partitioning methods that will be suitable for the 3D component designs. Net lists partitioning is a key aspect of the physical design of a 3D IC. Reducing wire lengths between gates is possible with 3D-ICs since they have a small footprint as well as vertical connectivity among dies. As a result, they consume less power and have shorter connection delays. This paper presents an efficient genetic algorithm (GA) based layer partitioning technique for 3D ICs that focuses on proper layer assignment to reduce area deviation and minimization of Through Silicon Vias (TSVs) to reduce IC footprint. The method starts with random initial solutions and refines the solutions with efficient crossover and mutation operator till the optimized solution is achieved. Our methodology produces high-quality solutions on well-known benchmarks. The experimental findings are compared with state-of-the-art methodologies and the suggested strategy is found to be very effective in the case of decreasing the TSV count and space need of the 3-dimensional IC design. In addition, the performance of our strategy is also compared with two recent publications that use GA and Particle Swarm Optimization (PSO) and it is found that the proposed method achieves 20.18% and 38.66% average reduction in terms of TSV count respectively. Thus, the suggested technique is beneficial for multilayered 3D IC partitioning, as it can reduce TSV count while also satisfying balancing criteria and latency.

Three-dimensional integration circuit (3D IC) offers significant benefits in terms of performance and cost. Existing research in through-silicon via (TSV)-based 3D IC partitioning has focused on minimizing the number of TSVs to reduce costs. Partitioning methods based on heterogeneous integration have emerged as viable approaches for cost optimization. Leveraging mature processes to manufacture not timing-critical blocks can yield cost benefits. Nevertheless, none of the previous 3D partitioning work has focused on reducing the overall cost, including both design and manufacturing costs, for heterogeneous 3D integration. Moreover, throughput constraints have not been considered. This article presents a cost-aware integer linear programming-based formulation and a heuristic algorithm that partition the functional blocks in the design into different technological groups. Each group of functional blocks will be implemented using a particular process technology, and then integrated into a 3D IC. Our results show that 3D heterogeneous integration chip implementation can reduce overall cost while satisfying various timing constraints.

Three-dimensional (3D) ICs using TSVs are the most promising candidate for high performance and low power computing since they have lots of advantages such as short wiring length, small chip size, and small pin capacitances, as shown in the paper. Until now, several kinds of 3D-ICs including image sensor chip, shared memory, and retinal prosthesis chip have been fabricated successfully. As for reliabilities of 3D-IC s with TSVs, however, several issues still remain prior to volume productions. In general, there are millions of TSVs and metal microbumps in vertically stacked thinned Si chips. Therefore, electrical characteristics of 3D-ICs are affected by such structures. The paper shows reliability issues in 3D-IC with TSVs. Both TSVs and metal microbumps cause local mechanical stress and strain in stacked thinned Si chips due to coefficient of thermal expansion (CTE) mismatch between Si and Cu TSV and metal microbump. As the thickness of Si chip has to be reduced less than several tens of μm, this might cause residual stress and crystal defects in the thinned Si chip. In addition, both intrinsic and extrinsic gettering layers to suppress metal contaminations and crystal defects might be eliminated from the Si chip by thinning process. This paper focuses on the most potent reliability issues such as Cu contamination and thermomechanical stress, and discusses new evaluation methods for the issues.

Temperature distributions in three dimensional (3D) ICs were analyzed with a thermal simulation and compared with measured results of test 3D ICs, in which sensor p-n diode arrays and on chip heaters were embedded. The 3D IC consists of a top tier test chip and a 410 um thick bottom dummy chip. Both top tier chips and bottom dummy chips were fabricated by a standard 0.18 um CMOS process. The top tier chips had four kinds of the thickness of 50 through 410 um. The temperature distributions of the top tier test chip under the constant heater power were analyzed by both measurements and thermal simulations. The thinner top tier structures showed the higher temperature and affected the temperature distributions. Effect of various boundary conditions such as substrate size and peripheral bonding pads were examined with thermal simulation. The test structure and the simulation modeling can provide an effective way for analysis of thermal conduction in 3D ICs.

The threat of food safety and the limited analytical methods with high performance promote the growing interest in the development of pathogenic bacteria biosensors. This study presents a pathogenic bacteria biosensing system, where a novel three-dimensional (3D) chip acts as an analytical carrier and DNA-programmed hybridization chain reaction (HCR) causes signal amplification. The 3D chip is designed featuring a compact multichannel structure. It has a large surface area for sensitive sensing and exhibits multiple functions of target capture, separation, rinsing, and signal detection to simplify the analysis processes. HCR, which enables the fluorophore's polymerization, is designed as two signal amplification modes, each with unique advantages. Mode I achieves highly sensitive detection in a "sandwich" assay format, in which a long HCR-amplified probe is used to boost the fluorescence signal. In mode II, the assembly of HCR is performed on the inner surface of the 3D chip. Especially, a group of rapid-assembly HCR sequences is proposed, of which the assembly time as short as 15 min stands out among the related works previously reported. Under the optimal conditions, the proposed biosensing system has the limits of detection (LOD) of 4 and 8 cfu/mL in mode I for Staphylococcus aureus detection and in mode II for Salmonella enterica Typhimurium detection, respectively. The specificity and the real sample applications are evaluated. This multichannel-structured 3D chip based on HCR signal amplification has potential applications in food safety monitoring and biosensor development.

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10–20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to non optimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products.

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

3D IC integration is very important to overcome the technology scaling barriers and to satisfy mobile devices' demand. In this paper, we describe the challenges we are facing in developing 3D IC design methodology, especially in the case of TSV-SiP (Logic-Memory die stacking). Also, appropriate development approaches are proposed. The EDA tools for TSV-SiP, which are initially provided by extending current conventional tools, will be gradually enhanced to better support 3D IC designs.

In last few decades, the semiconductor industry has advanced as Moore's law predicted. With the introduction of 3D IC, it has extended the Moore's law into another dimension.The 3DIC vast interconnecting capabilities and ultra-short die to die distance can be fully explored for high bandwidth, low power applications. These 3D IC's are capable of enhancing overall chip performance and achieving high density heterogeneous system integration by utilizing through-silicon-vias (TSV), multiple die can be 3D stacked and/or stitching through Interposer into 3DIC platform. With the 3DIC memory family become standard last year, this also made a full computer system within 3DIC.Here we shall introduce one of test vehicles using TSMC CoWoS(tm) platform and using one of the JEDEC standard WideIO DRAM. We shall use it as example to explore 3DIC system advantages, design for test challenges and proposed solutions. Also we shall share a brief lesson learned from this Test Vehicle as well as some suggestions for future considerations.

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and

Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices.

For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. At SemiTherm2011, the equivalent thermal conductivity of the interconnection, including BEOL (Back-End-Of-the-Line, wiring layer) is experimentally obtained to be 1.6W/mC and this time, we measure the thermal effect of Cu TSVs and it is experimentally supported that as the Cu TSV area ratio increases, the thermal conductivity of chip with TSVs in the vertical direction increases, on the contrary, that in the horizontal direction decreases. Also, the transient thermal measurement is performed and its result is compared with steady state measurement result. Further, the thermal capacitance measurement of 3D stacked test chip with hot spot heating is performed, which is essential to determine the transient thermal performance of 3D chip stack.

With the advancement of 3D IC technology, multilayer chip stacking enables improved performance and reduced power consumption, albeit at the cost of increased design complexity. In 3D IC designs, soft modules are also adopted to enable flexible floorplanning across multiple dies. To preserve module integrity and simplify interconnects, the standard cells and macros within the same module are typically constrained to be placed on the same layer and thus using the same technology. In addition, determining an appropriate shape and placement location for each soft module is critical for minimizing wirelength. This paper presents the first technology-aware 3D placement framework for mixed-size designs that incorporates region planning for soft modules. It combines an analytical placement engine with an integer linear programming (ILP)-based region planning strategy to handle the flexible nature of soft modules. To further enhance placement flexibility while limiting region complexity, the ILP formulation identifies an optimal L-shaped or rectangular region for each soft module. Experimental results demonstrate that, compared to a baseline approach, our flow achieves over 21% wirelength reduction, with only a 5% overhead compared to placement without the soft module constraint.

3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads to nonuniform temperature rises. Elevated local temperatures can change carrier mobility, relax mechanical stress, and affect material deformation behaviors. Consequently, these local temperature rises can affect device performance, structure integrity, and material reliability. To accurately assess these thermal and mechanical effects, extract design rules, optimize designs, and develop performance and reliability mitigation methodologies, it is of paramount importance to characterize material deformation and interface de-bonding behaviors, map chip temperature distributions, and analyze stress hotspot evolutions during integration process and under operation conditions while developing 3D IC integration technologies [1].In this study, a multiscale hierarchical modeling approach is assembled to analyze thermal, mechanical, and material deformation and interface de-bonding behaviors under 3D integration process and operation conditions for a newly designed 3D IC package with a 2nm SOC die copper-bonded on an RDL interposer [2]. The 3DIC structures are constructed directly using GDSII design and ITF technology data [3]. Each structural layer is divided into small smear tiles. Each tile is represented by anisotropic thermal and mechanical properties that depend on local feature patterns in the tile. Under given operation conditions, power grids are generated and used as heat sources for thermal analysis. For multiscale hierarchical modeling, the global thermal and mechanical analyses that call for coarse grain resolution are first performed. The subsequent local analyses that provide fine grain resolution in areas of interests utilize boundary conditions that are extracted from the global analyses. The material deformation and interface de-bonding behaviors are simulated using molecular dynamics [4]. Several 3D integration design options are explored. The 3D configuration effects on chip temperature distributions during operations, stack warpages, silicon mobility variations, and chip package interaction induced stress hotspots are examined. The elevated temperature impacts on material deformation and de-bonding process are also investigated.