3D-IC technology and reliability challenges

Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. However, when deciding to adopt this emerging technology as a mainstream design approach, designers must consider the cost of 3D integration. IC testing is a key factor that affects the final product cost, and it could be a major portion of the total IC cost. In 3D IC design, various testing strategies and different integration methods could affect the final product cost dramatically, and the interaction with other cost factors could result in various trade-offs. This paper develops a comprehensive and parameterized testing cost model for 3D IC integration, and analyzes the trade-offs associated with testing strategies and testing circuit overheads. With the proposed testing cost model, designers can explore the most cost-effective integration and testing strategies for 3D IC chips.

With the rapid advance of enabling technologies, the era of 3D ICs is near. Yet, there are several practical problems to be solved for 3D ICs. Especially, heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. Recently, liquid cooling based on micro-fluidic channels is proposed as a viable solution to dramatically reduce the temperature of 3D ICs. In addition, a highly complex power distribution network is required to deliver currents to all parts of the 3D IC stack while suppressing power noise to an acceptable level. These technologies pose major challenges to signal routing. With a given amount of silicon area, signal, power, and thermal interconnects compete against one another for routing space. This paper presents an optimization study on signal, power, and thermal networks in 3D ICs. We demonstrate how to optimize various design parameters by adopting design of experiments and response surface method.

The rise of three-dimensional (3D) IC layouts necessitates the development of unique partitioning methods that will be suitable for the 3D component designs. Net lists partitioning is a key aspect of the physical design of a 3D IC. Reducing wire lengths between gates is possible with 3D-ICs since they have a small footprint as well as vertical connectivity among dies. As a result, they consume less power and have shorter connection delays. This paper presents an efficient genetic algorithm (GA) based layer partitioning technique for 3D ICs that focuses on proper layer assignment to reduce area deviation and minimization of Through Silicon Vias (TSVs) to reduce IC footprint. The method starts with random initial solutions and refines the solutions with efficient crossover and mutation operator till the optimized solution is achieved. Our methodology produces high-quality solutions on well-known benchmarks. The experimental findings are compared with state-of-the-art methodologies and the suggested strategy is found to be very effective in the case of decreasing the TSV count and space need of the 3-dimensional IC design. In addition, the performance of our strategy is also compared with two recent publications that use GA and Particle Swarm Optimization (PSO) and it is found that the proposed method achieves 20.18% and 38.66% average reduction in terms of TSV count respectively. Thus, the suggested technique is beneficial for multilayered 3D IC partitioning, as it can reduce TSV count while also satisfying balancing criteria and latency.

Reliability challenges in 3D IC packaging technology

As technology advances, 3D ICs is introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the key challenges is the vertical interlayer via used for different device layers connection. In this paper, we use min-cost maximum flow algorithm for integrated interlayer via planning and pin assignment for all two-pin nets from one source block to all the other blocks, which make sure interlayer via is inserted as successfully as possible with the shortest wire length. By iteratively using this algorithm with other auxiliary methods on each block, we can deal with the problem for all nets among blocks in 3D ICs. Experimental results show its efficiency and effectiveness. To our knowledge, this is the first algorithm of interlayer via planning with pin assignment for 3D ICs.

3D IC technologies are now approaching the innovation and business activities of semiconductor industries. 3D IC can be heterogeneous from different chip, interposer or substrate to integrate into a single package by using through silicon via (TSV) technique. With increasing functionality and performance at minimum cost and power dissipation, wide I/O memory VLSI technologies are being aggressively scaled to meet this demand. Stack memory chips using TSV technique will lead to increase a significant manufacturing challenge for semiconductor industries. TSV formation and interconnected reliability on the intermetallic compound (IMC) between the metal-metal bounded micro-bumps are crucial for 3D IC technologies. As the number and power of IC increases, lots of heat will be generated and, in turn raises the junction temperature. This will greatly deteriorate the performance of IC. Heat dissipation for 3D IC, when the power density exceeds 100W/cm2, is an important design concern before marketing. In this paper, high density TSV formed by an ultrafast pico-second laser to evaluate the behavior between manufacturing process and silicon material is presented. In addition, thermal management using finite element analysis to predict the reliability of TSV model is demonstrated.

Temperature distributions in three dimensional (3D) ICs were analyzed with a thermal simulation and compared with measured results of test 3D ICs, in which sensor p-n diode arrays and on chip heaters were embedded. The 3D IC consists of a top tier test chip and a 410 um thick bottom dummy chip. Both top tier chips and bottom dummy chips were fabricated by a standard 0.18 um CMOS process. The top tier chips had four kinds of the thickness of 50 through 410 um. The temperature distributions of the top tier test chip under the constant heater power were analyzed by both measurements and thermal simulations. The thinner top tier structures showed the higher temperature and affected the temperature distributions. Effect of various boundary conditions such as substrate size and peripheral bonding pads were examined with thermal simulation. The test structure and the simulation modeling can provide an effective way for analysis of thermal conduction in 3D ICs.

The threat of food safety and the limited analytical methods with high performance promote the growing interest in the development of pathogenic bacteria biosensors. This study presents a pathogenic bacteria biosensing system, where a novel three-dimensional (3D) chip acts as an analytical carrier and DNA-programmed hybridization chain reaction (HCR) causes signal amplification. The 3D chip is designed featuring a compact multichannel structure. It has a large surface area for sensitive sensing and exhibits multiple functions of target capture, separation, rinsing, and signal detection to simplify the analysis processes. HCR, which enables the fluorophore's polymerization, is designed as two signal amplification modes, each with unique advantages. Mode I achieves highly sensitive detection in a "sandwich" assay format, in which a long HCR-amplified probe is used to boost the fluorescence signal. In mode II, the assembly of HCR is performed on the inner surface of the 3D chip. Especially, a group of rapid-assembly HCR sequences is proposed, of which the assembly time as short as 15 min stands out among the related works previously reported. Under the optimal conditions, the proposed biosensing system has the limits of detection (LOD) of 4 and 8 cfu/mL in mode I for Staphylococcus aureus detection and in mode II for Salmonella enterica Typhimurium detection, respectively. The specificity and the real sample applications are evaluated. This multichannel-structured 3D chip based on HCR signal amplification has potential applications in food safety monitoring and biosensor development.

This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and

This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.

With the rapid development of IC technologies, topics of 3D stacked IC packages are now being studied vastly around the world. In 3D stacked IC technologies, many electrical characteristics have been proved to have great improvements, but their corresponding thermo-mechanical problems are raising as well. Due to the reason of ICs stacking, thermo-mechanical problems are becoming more serious than those in traditional single IC package. These problems include the heat dissipation, die breaking, interfacial delamination, via cracking and so on. These corresponding problems not only cause failures in 3D stacked IC packages but also have significant influences on reliability. For the sake of realizing critical stress distributions in 3D stacked IC packages, the three dimensional finite element analysis (FEA) modeling has been employed in this paper. The 3D-WLP (wafer-level-package) with ten layer chips stacking is selected as our test vehicle. By using three dimensional FEA modeling, thermal induced stress distributions in 3D-WLP when subjected to a uniform temperature change can be illustrated. Further, the design of experiments (DOE) analysis for design optimization has also been used to obtain the sensitivities of geometry and material properties of 3D-WLP. Several geometric dimensions and material properties are selected as main design factors and the average value of maximum von Mises stress in copper vias and chips is chosen as the response to be optimized. Through the DOE analysis, the optimum geometry and material properties of 3D-WLP and this result in smaller von Mises stresses in copper via and chip configurations can be obtained. These results can be most effectively used as design guidelines to engineers when optimum stress solutions in 3D-WLP are required.

3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.

Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSV's, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.

Two RF techniques are combined with capacitive coupling interconnect to form ultra-wide-bandwidth impulse interconnect and RF interconnect in 3D IC technology. They achieve 10Gb/s/pin and 11Gb/s/pin transmission with 2.7mW/pin and 4.35mW/pin power consumption, respectively, using the MIT Lincoln Lab 3D 0.18mum CMOS, an 8times improvement over previous work