2.5D and 3D technology challenges and test vehicle demonstrations

In recent years, digital VLSI circuits operating under sub-threshold operation have gained a lot of attention due to the rapid growth in technology from low to high performance applications. In addition to that, performance is improved by device dimensions and circuit operations under threshold regime. This leads to promising technology for future memory designs for ultra-low power applications. On the other hand, there is an issue of static or leakage current that leads to a reduction of performance. Novelty of research in the paper described the design and implementation of energy efficient SRAM designs such as Saturated NMOS SRAM, Schmitt trigger-based SRAM’s working under sub-threshold for ultra-low power applications by measuring leakage power. Both logic, circuit and architecture level designs have extensively analyzed to evaluate the performance and functionality of SRAM designs. Comparative analysis is made on the basis of read, write performance, SNM, along with the functionality of static, dynamic characteristics.KeywordsSaturated NMOSSchmitt trigger SRAMSub-thresholdStatic currentLow power

FinFET transistors have great advantages over traditional planar MOSFET transistors in high performance and low power applications. Major foundries are adopting the Fin-FET technology for CMOS semiconductor device fabrication in the 16 nm technology node and beyond. Edge device degradation is among the major challenges for the FinFET process. To avoid such degradation, dummy gates are needed on device edges, and the dummy gates have to be tied to power rails in order not to introduce unconnected parasitic transistors. This requires that each dummy gate must abut at least one source node after standard cell placement. If the drain nodes at two adjacent cell boundaries abut each other, additional source nodes must be inserted in between for dummy gate power tying, which costs more placement area. Usually there is some flexibility during detailed placement to horizontally flip the cells or switch the positions of adjacent cells, which has little impact on the global placement objectives, such as timing conditions and net congestion. This paper proposes a detailed placement optimization strategy for the standard cell based designs. By flipping a subset of cells in a standard cell row and switching pairs of adjacent cells, the number of drain to drain abutments between adjacent cell boundaries can be optimally minimized, which saves additional source node insertion and reduces the length of the standard cell row. In addition, the proposed graph model can be easily modified to consider more complicated design rules. The experimental results show that the optimization of 100k cells is completed within 0.1 second, verifying the efficiency of the proposed algorithm.

FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.

90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical stability. To accomplish these purposes, we develop the multi-stack storage node structure whose enlarged bottom size of OCS(One Cylindrical Storage node) can give much better mechanical stability of the capacitor than that of the conventional capacitor. Using Al/sub 2/O/sub 3//HfO/sub 2/ dielectric material together with this structure can give high cell capacitance 30fF/cell and low leakage current less than 1fA/cell.

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node

This paper introduces new controls for the cascaded multilevel power converter. This converter is also sometimes referred to as a ldquohybrid converterrdquo since it splits high-voltage/low-frequency and low-voltage/pulsewidth-modulation (PWM)-frequency power production between ldquobulkrdquo and ldquoconditioningrdquo converters respectively. Cascaded multilevel converters achieve higher power quality with a given switch count when compared to traditional multilevel converters. This is a particularly favorable option for high power and high performance applications such as naval ship propulsion. This paper first presents a new control method for the topology using three-level bulk and conditioning inverters connected in series through a three-phase load. This control avoids PWM frequency switching in the bulk inverter. The conditioning inverter uses a capacitor source and its control is based on compensating the real and reactive (P-Q) power difference between the bulk inverter and the load. The new control explicitly commands power into the conditioning inverter so that its capacitor voltage remains constant. A unique space vector analysis of hybrid converter modulation is introduced to quantitatively determine operating limitations. The conclusion is then generalized for all types of controls of the hybrid multilevel converters (involving three-level converter cells). The proposed control methods and analytical conclusions are verified by simulation and laboratory measurements.

Many embedded processor chips aimed at high performance and low power application domains are implemented as multiprocessor System-on-Chip (MPSoC) devices. The multimedia and communication sub-systems of an MPSoC perform some of the most computation intensive and performance critical tasks, and are key determinants of the system-level performance and power consumption. This paper presents an automated technique for synthesizing the system-level memory architecture (both code and data) for the streaming sub-systems of an embedded processor. The experimental results evaluate effectiveness of the proposed technique by synthesizing the system-level memory architecture for benchmark stream processing applications and comparisons against an existing approach.

We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

In this paper, a high throughput and low power architecture for 256-point FFT processor is proposed which is suitable for both high performance and low power applications. The proposed architecture is based on Radix-4 algorithm. We choose pipelined Multi-path Delay Commutators (MDC) for our design. Two separate datapaths are used in this architecture so that it can process eight inputs in parallel. Thus, the throughput is increased by eight times while achieving 100% hardware utilization. Power consumption of this architecture is shown to be about 50% less than a regular Radix-4 MDC structure for a same throughput. We implement our design in Xilinx FPGA Virtex 5 and compare with regular R4MDC for area, throughput, and power.

The design of efficient multiprocessor systems on chip (MPSoC) is a daunting challenge. This challenge is driven by the increasing demand in achieving high performance, low power, and reconfigurable applications onto the same platform. As a consequence, there is an emerging need for fast, and efficient design space exploration, while providing abstract models for a wide range of applications, and types of processing units (PUs). Therefore, this paper proposes a framework for a fast MPSoC generation with joint task and core mapping with the objective of minimizing the average power consumption. The proposed framework considers the static, dynamic, reconfiguration and communication power components. A tool for high level MPSoC task and core mapping (MPMAP) is built based on the proposed framework. MPMAP provides a flexible XML interface that provides a high level description of the different PU architectures, and different applications scenarios. Additionally, the paper presents a case study of real-life applications that can be adopted in future heterogeneous wireless systems.

This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.

This paper presents the comparative study of multiple output inverter topologies in terms of their circuit operation, control techniques, output power, number of switches required and their efficiency. It includes the concept of multi-output inverter for IH applications. Two multi-output topologies are explained for high power and low power applications. These topologies allow higher efficiency, low cost and less switching losses as compared to other multiple output techniques such as paralleled power converters and load-multiplexation technique. The control strategy includes asymmetrical voltage cancellation (AVC), Variable frequency duty cycle (VFDC) and Pulse density modulation (PDM) control techniques. The performance of multiple-output inverter topologies is verified using MATLABSimulink.

Solid-state buck converters are popular for regulating output voltages of switch-mode dc power supplies for various applications. An output filter inductor in a buck converter is one of the crucial components to provide a continuous load current when the switching devices in the buck converter, such as BJTs, FETs, MOSFETs, or IGBTs, turn off. This inductor can be purchased as a commercial-off-the-shelf (COTS) component for a converter with a low voltage and power application. In a low voltage and high power application, it is still available through a number of vendors in the magnetic component industry. However, for a gyrotron cathode power supply in electron cyclotron heating (ECH) for fusion energy research [1] with an input voltage of 120 kV and output voltage of 80 kV at a load current of 100 Amperes, it is very difficult to obtain such an inductor from a qualified vendor. Two 15 mH inductors at a load current of 100 Amperes were designed and built inhouse to meet the required input and output voltages. The design strategy, method of construction, and insulation test results of these inductors will be discussed in this paper.

In the practical requirement for high-efficiency, high power density and high-performance in the switched-mode power supplies and their related application systems, a variety of circuit topologies of DC-DC converters incorporating soft-switching PDM, PFM and PWM control schemes have attracted special interest in the fields of low power and high power applications. Some types of quasi-resonant soft-switching PWM converters have remarkable advantages such as lowered switching losses of power semiconductor devices, reduced dynamic electrical stresses, constant frequency operation, simple control scheme as well as reduced EMI noise.However, most of soft-switched quasi-resonant PWM converters developed so far include some inherent items which have to be solved such as reduced power conversion efficiency due to significant circulating current generation. In recent years, the newly modified prototype of soft-switched PWM DC-DC converter with a high-frequency transformer link has been proposed, which is capable of excluding circulating current operation mode.This paper presents a novel high-frequency transformer link soft-switching PWM DC-DC converter using active switches in rectifier circuit. Its operating principle and unique features are described as compared with the previously developed DC-DC converter. Operating performance of this converter in steady-state are illutrated and disccused including the simulated analytical and experimental results.

With the constant scaling down of transistors, “More Moore” has put forward requirements for channel materials. Two-dimensional materials are considered as potential next-generation channel materials due to their unique physical properties. Herein, we study the ballistic transport characteristics of sub-10 nm monolayer (ML) planar GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) based on density functional theory and the non-equilibrium Green's function method. The calculation results indicate that n-type ML planar GaN MOSFETs with gate lengths not less than 5 nm exhibit excellent subthreshold characteristics, fast switching speeds, and low switching energies, and the corresponding parameters (off-current, on-current, delay time, and power-delay product) can simultaneously meet the requirements of the International Roadmap for Devices and Systems for the 2028 horizon for high-performance and low-power applications. Therefore, ML planar GaN is predicted to be a reliable next-generation channel material to extend Moore's law.