A universal testability strategy for multi-chip modules based on BIST and boundary-scan

Products motivated by performance-driven and/or density-driven goals are utilizing Multi-Chip Module (MCM) technology. However, this technology still has several challenging problems that need to be resolved before it becomes a widely adopted solution. One of the critical problems is meeting the quality requirements of MCM manufacturing, and hence reaching acceptable MCM assembly yields. This can be achieved by adopting a testing strategy, that first guarantees the quality of incoming bare dies and expensive substrates prior to module assembly, then ensures the functionality and performance of the assembled MCMs, and finally helps isolating the defected parts prior to the rework process. This paper presents a testability strategy that can be implemented mainly by incorporating Built-in Self-Test (BIST) and Boundary-Scan during the chip design cycle. And based on which the paper demonstrates the testing and diagnosis procedures needed to meet the above duality target. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate or attachment technologies adopted to build the MCM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10–20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to non optimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products.

Products motivated by performance-driven and/or density-driven goals have started to use multi-chip module (MCM) technology, even though this technology still has several challenging problems, that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable MCM assembly yields and meeting product quality requirements. Both of these problems can be significantly reduced by adopting adequate testing. Approaches which guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, ensure the structural integrity and performance of the assembled MCMs, and help isolating defective parts prior to the repair process. This paper presents a structured testability approach that helps resolve the above problems. The approach can be adopted during MCM design and utilized during the manufacturing process. It is based on adopting Built-In-Self-Test (BIST) and boundary-scan and is in general independent of silicon, substrate or attachment technologies, hence it can be considered a generic solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The author describes a system-level built-in test architecture and illustrates how system designers can interface to boundary (and other) scan devices on boards to facilitate line replaceable unit and system-level built-in test, online monitoring, and fault isolation using both serial and real-time techniques. He also shows how to bridge the protocol gaps between the various scan design devices (e.g. LSSD, boundary scan, and VHSIC) to arrive at an integrated built-in test and diagnostics strategy. It is concluded that the only way to achieve the fault detection and fault isolation requirements for the system is to design each card to be fully testable. Each designer could configure the circuit in any way desired and use any mix of components. The only rule is to have testability circuitry that can communicate with a standard testability bus interface on each card so that the system BIT (built-in-test) processor can perform its tasks. >

A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Summary form only given. The authors discuss the fundamental issues confronting designers and manufacturers of the multichip modules (MCMs). All of them ultimately determine the product cost, be it the in-process and final test yields, the engineering effort in design and manufacturing support, or the MCM quality and reliability. Challenges are compounded in a situation where MCMs are assembled with chips and/or substrates obtained from an outside supplier. Issues range from the design groundrules to the lack of (comprehensive) standards, to the question of responsibility for assurance of quality and reliability, to the profit margins potentially reduced by shipping unpackaged chips. The initial driving force for MCMs has been the improved performance over the SCMs facilitated by the reduced interchip wiring delays. In this decade, all high end mainframes employ MCMs capable of carrying as many as 144 chips and handling up to 4.5 kW. Another driving force is the volume and weight reduction, and the reliability enhancement achievable with silicon-on-silicon MCMs. The growing pinout demand of all but the memory chips pushes the SCM packaging costs beyond those deemed possible with the MCMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A family of high performance, computer oriented multichip module (MCM) products is being developed to provide the building blocks for advanced, high density computer systems. Each MCM is a system level building block that interfaces to other family members through compatible processor and memory busses. By selecting and interconnecting the various MGM blocks, it is possible to configure a variety of high speed, cache coherent, multiprocessing computer designs. The use of multichip modules is necessary to meet system performance and size requirements. This paper focuses on a specific member of the MGM family, a 4M word by 40 bit Dynamic Random Access Memory (DRAM). Special attention is given to product requirements, design methodology, and test strategy. MCM testing is sufficiently complex that test must be an integral part of the complete module design process.

Three ASIC (application-specific integrated circuit) devices recently designed at AT&T incorporate the ANSI/IEEE Std 1149.1-1990 testability features. The test port is used for control of on-chip boundary-scan (BS) and full chip (macrocell and random logic) built-in-self-test (BIST). Presented are a view of the methods used for implementation, novel circuit sharing between BIST and BS, and results related to device area, performance, fault coverage, and testing. The availability of boundary-scan allowed automatic generation of board-level test vectors and allowed board-level printed wire testing without bed-of-nails techniques. By applying BIST tools to the devices after functional design, fault coverage of all of the ASICs was increased to acceptable levels without the significant time and expense of manual vector writing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design for testability (DFT) help in simplifying the ‘manufacturing tests’ used to detect post fabrication manufacturing defects in an integrated circuits (IC). The embedded memory tests in an integrated circuits utilize Built In Self Test (BIST) strategy. In this paper we have shown BIST technique and several algorithms used in BIST to test embedded memory. Such memory BIST technique comprises of address generator, controller, comparator and memory. The work presents the three different algorithms for implementing controller used in the memory BIST. The modeling of the memory BIST controller is performed using Verilog HDL to verify correctness of these memory controllers which are then synthesized using RTL compiler utilizing TSMC 90 nm and ARM 7 nm technology library. The paper shows the comparisons of area, power and timing results obtained from RTL compiler for these controller.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

The increasing complexity of microelectronic circuitry, as witnessed by multi-chip modules and system-on-a-chip and the rapid growth of manufacturing process automation, require that more effective and efficient testing and fault diagnosis techniques be developed to improve system reliability, reduce machine down time, and enhance productivity. As a design philosophy, built-in-test (BIT) is receiving increasing attention from the research community. This paper presents an overview of BIT research in several areas of industry, including semiconductor, manufacturing, aerospace and transportation.

This paper describes the C-17A mission computer (MC) internal built-in test (BIT) and intermediate level (I-Level) fault logging strategies. The MC is the primary component of the C-17A mission computer/electronic display subsystem (MC/EDS). The MC/EDS is intended to provide flight management functions for the C-17A aircraft in addition to display processing and display of mission, flight, engine, aircraft status and other related information to the flight crew. The MC is designed to be a highly reliable and fail-safe computer to prevent inadvertent display of hazardously misleading information on the head-up and head-down displays. The MC subsystem uses triple modular redundancy and voting schemes to detect the failures and isolate them to a line replaceable unit (LRU). The fault detection circuits in the MC detect the faults concurrently with the normal operation and report them to the MC CPU. The self-test programs are comprised of separately executing software/firmware modules. These modules when combined with the BIT hardware achieve a high degree of fault detection coverage. In this paper we present the MC internal BIT modes such as power-up, periodic, and initiated BIT. The software BIT mechanisms are discussed and the MC I-level fault logging approach is reviewed. >

As today's electronics systems increase in complexity, techniques allowing access to "low level" test resources (built-in self-test, boundary scan) are crucial for developing high fault coverage tests. Two IEEE test bus protocol standards have been defined to provide this access at the module (IEEE 1149.5) and device levels (IEEE 1149.1), respectively. This paper discusses the IEEE 1149.5 standard's proposed method for interfacing to the IEEE 1149.1 boundary scan and the issues associated with this interfacing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This papers analyzes the ways that physical scaling of electrical interconnecting structures impacts their delays, with particular focus on multichip modules. We use for illustration example structures typical of laminate and thin-film based MCMs. Because multichip modules have higher packaging densities than conventional packaging, loading plays a correspondingly more important role in their delays. The most important parameters dominating the performance of MCMs are the average distance between the chips (i.e. the packaging density), the size of the load capacitance and the number of loads connected to the line. Focusing attention on these areas has the greatest potential to improve MCM performance, regardless of the particular substrate technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. However, when deciding to adopt this emerging technology as a mainstream design approach, designers must consider the cost of 3D integration. IC testing is a key factor that affects the final product cost, and it could be a major portion of the total IC cost. In 3D IC design, various testing strategies and different integration methods could affect the final product cost dramatically, and the interaction with other cost factors could result in various trade-offs. This paper develops a comprehensive and parameterized testing cost model for 3D IC integration, and analyzes the trade-offs associated with testing strategies and testing circuit overheads. With the proposed testing cost model, designers can explore the most cost-effective integration and testing strategies for 3D IC chips.