BIT for intelligent system design and condition monitoring

The rapid growth of process automation requires that more efficient and reliable system testing and fault diagnosis techniques be developed to reduce machine down time and enhance productivity. As a design philosophy built-in-test (BIT) is receiving increasing attention. This paper presents an overview of diverse BIT applications in several areas of industry, including manufacturing, aerospace, and transportation.

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10–20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to non optimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products.

A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM. >

The increased circuit complexity of field programmable gate array (FPGA) poses a major challenge in the testing of FPGAs. One of the test challenges is to detect the delay faults in high‐speed circuits. Built‐in‐self‐test (BIST) Technique is an ease solution compared with expensive automatic test equipment. In this work, a BIST structure is proposed to detect the delay faults in the various resources of the FPGA such as multiplier, digital signal processing (DSP) block, look‐up tables etc. and interconnects of FPGA. The authors have also proposed a full‐diagnosable BISTer structure that improves the testing efficiency of the logic BIST. The proposed BISTer structure can diagnose the faulty configurable logic block (CLB), when all the CLBs in the 2 × 3 BIST are faulty. The proposed scheme has been simulated in Xilinx Vertex FPGA, using ISE tool, Jbits3.0 API and XHWI (Xilinx HardWare Interface) and MATLAB7.0. The result shows significant improvement compared with earlier BIST methods.

Products motivated by performance-driven and/or density-driven goals have started to use multi-chip module (MCM) technology, even though this technology still has several challenging problems, that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable MCM assembly yields and meeting product quality requirements. Both of these problems can be significantly reduced by adopting adequate testing. Approaches which guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, ensure the structural integrity and performance of the assembled MCMs, and help isolating defective parts prior to the repair process. This paper presents a structured testability approach that helps resolve the above problems. The approach can be adopted during MCM design and utilized during the manufacturing process. It is based on adopting Built-In-Self-Test (BIST) and boundary-scan and is in general independent of silicon, substrate or attachment technologies, hence it can be considered a generic solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

A comparative investigation of data-driven approaches based on one-class classifiers for condition monitoring of marine machinery system

Products motivated by performance-driven and/or density-driven goals are utilizing Multi-Chip Module (MCM) technology. However, this technology still has several challenging problems that need to be resolved before it becomes a widely adopted solution. One of the critical problems is meeting the quality requirements of MCM manufacturing, and hence reaching acceptable MCM assembly yields. This can be achieved by adopting a testing strategy, that first guarantees the quality of incoming bare dies and expensive substrates prior to module assembly, then ensures the functionality and performance of the assembled MCMs, and finally helps isolating the defected parts prior to the rework process. This paper presents a testability strategy that can be implemented mainly by incorporating Built-in Self-Test (BIST) and Boundary-Scan during the chip design cycle. And based on which the paper demonstrates the testing and diagnosis procedures needed to meet the above duality target. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate or attachment technologies adopted to build the MCM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Condition monitoring and management system (CMMS) for power transmission and distribution equipments is an important part of smart grid. This paper addresses issues relating to the techniques of CMMS and its application in Yunnan Power Grid. After introducing the basic concepts and essential characters of Intelligent CMMS, many technological challenging issues of it are discussed. And engineering research and application cases in Yunnan Power Grid for develop a fully perceptive smart are also introduced in detail, including the Data Supervise System (DSS), some original methods for faults diagnosis or disaster warning, and the research project about intelligent monitoring and full lifecycle management for power transmission and distribution equipments based on internet of things. Those are helpful to improve the reliability of power grid devices and ensure the safety of Yunnan Power Grid.

Increasing interest has been seen in condition monitoring (CM) techniques for electrical equipment, mainly including transformer, generator, and induction motor in power plants, because CM has the potential to reduce operating costs, enhance the reliability of operation, and improve power supply and service to customers. Literature is accumulated on developing intelligent CM systems with advanced practicability, sensitivity, reliability, and automation. A literature survey is felt necessary with an aim to reflect the state-of-the-art development in this important area. After introducing the concepts and functions of CM, this paper describes the popular monitoring methods for and research status of CM on transformers, generators, and induction motors, respectively. The paper also points out the potential benefits through the utilization of advanced signal processing and artificial intelligence techniques in developing novel CM schemes.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

The chapter aims to review literature in the area of Sustainable Manufacturing and Service Supply Chains in Industry 4.0 era. The survey aims to explore the literature growth on Industry 4.0, development of the theoretical framework and extending support to the practical implementation of Industry 4.0 in Service and Manufacturing setups. A noted list of 3,561 articles published during 1991-2018 are taken into consideration belong to various databases (viz. Web of Science and Scopus, that includes, Social Citation Index Expanded (SCI-Expanded), Social Science Citation Index (SSCI), Art and Humanities Citation Index (A&amp;HCI), Conference Proceedings, etc.). The surveyed documents shows state of art research in the area of Industry 4.0 and industrial transformation across Service and Manufacturing setups. We have varieties of Content Analysis Techniques, for present study Latent Semantic Analysis is used, due to its comprehensive nature and ability to a method to formulate latent factors (Joshi et al., 2017). LSA creates the scientific grounding to understand the trends. Using LSA, Understanding 98future research trends will assist researchers in the area of Manufacturing and Service Operations. Therefore, the study will be beneficial for practitioners of the strategic and operational aspects of technology adoption in Manufacturing and service supply chain decision making. The current chapter uses the LSA approach (Joshi et al., 2017). The whole chapter is bifurcated into four sections viz. the first section describes the introduction to the evolvement of technology adoption across supply chains. The second section describes the usage of LSA for current study. The third section describes the finding and results. The fourth and final sections conclude the chapter with a brief discussion on research findings, its limitations, and the implications for future research. The outcomes of analysis presented in this chapter also provide opportunities for researchers/professionals to position their future technology driven supply chain research AND/OR implementation strategies.

Perspectives on condition monitoring techniques of wind turbines

Electrical machines are prone to various faults and require constant monitoring to ensure safe and dependable functioning. A potential fault in electrical machinery results in unscheduled downtime, necessitating the prompt assessment of any abnormal circumstances in rotating electrical machines. This paper provides an in-depth analysis as well as the most recent trends in the application of condition monitoring and fault detection techniques in the disciplines of electrical machinery. It first investigates the evolution of traditional monitoring techniques, followed by signal-based techniques such as spectrum, vibration, and temperature analysis, and the most recent trends in its signal processing techniques for assessing faults. Then, it investigates and details the implementation and evolution of modern approaches that employ intelligence-based techniques such as neural networks and support vector machines. All these applicable and state-of-art techniques in condition monitoring and fault diagnosis aid in predictive maintenance and identification and have the highly reliable operation of a motor drive system. Furthermore, this paper focuses on the possible transformational impact of electrical machine condition monitoring by thoroughly analyzing each of the monitoring techniques, their corresponding pros and cons, their approaches, and their applicability. It offers strong and useful insights into proactive maintenance measures, improved operating efficiency, and specific recommendations for future applications in the field of diagnostics.

The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.