A new framework for designing: built-in test multichip modules with pipelined test strategy

In this paper we present a new BIST test pattern generator architecture and a methodology to program this architecture to generate tests for any given inter-chip interconnect circuitry via IEEE 1149.1 boundary-scan architecture. The test architecture uses two test pattern generators, a C-TPG that generates test patterns for the control cells in the boundary scan chain and a D-TPG that generates rest patterns for the data cells. The other main component of the test architecture is a lookup table which is programmed to select, for each boundary scan cell, a specific C-TPG or D-TPG stage whose content is shifted into that cell. This test architecture provides a complete BIST solution for interconnect testing. The proposed BIST TPG design procedure uses the notions of incompatibility and conditional incompatibility and generates TPG designs that (i) guarantee that no circuit damage can occur due to multi-driver conflicts, (ii) guarantee the detection of all interconnect faults, (iii) have low area overhead, and (iv) have low test length. The proposed procedure is used to obtain TPG designs that require significantly less test time and area than other TPG designs, for eight interconnect circuits extracted from industrial boards.

A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM. >

Boundary Scan is being added to the manufacturing test strategy. With no experience, where do you start? An organization venturing into this new territory must adopt changes in Test and Design processes to achieve a successful implementation as an enhancement to board test. Highlighting the benefits for the effort is key to getting buy-in from all groups involved from concept to product, especially the Design group. As experience is gained, less interaction between groups is required to implement Boundary Scan, but that relationship can never be severed without compromising the design or manufacturability. Addressing the issues of Design For Test (DFT) early in a product life-cycle will prevent costly oversights and mistakes. A methodical approach is necessary to design in Boundary Scan testability. Very complex designs can require significant design effort during schematic capture that hardware developers are not accustomed to providing. Often times, complex IC access points for developers share pins with the IEEE 1149.1 Test Access Port (TAP). Care must be taken to prevent a manufacturable Boundary Scan design from disabling a design debug port (and vice versa), requiring close coordination between Test and Development during this phase of the design. In addition, both groups must deal with the requirements for signal integrity so that test and programming time targets can be achieved. Solutions may include dedicated Boundary Scan components designed into the product and test fixture. Upon schematic completion, generation of test and programming vectors follows. (Vectors are the logic bits that are loaded into the Boundary Scan registers – taken from the term for a one-dimensional array.) The Automatic Test Pattern Generator (ATPG) tool must be capable of handling the specific requirements of your design such as programming of persistent memory and management of partitioning devices. Details of vector generation are beyond the scope of this discussion, however care and effort to ensure a match between the design netlist and physical manufacturing to achieve maximum test coverage may require changes to the development and production cycle of a new design and should be considered in scheduling resources. Bringing all of the prior efforts together to test a product doesn't complete the process. Deficient Boundary Scan implementations in ICs and oversights in the design can result in significant delays during the test of initial prototypes, delays that have never been experienced in a test cycle. These must be overcome through interaction with the part suppliers and the design group, and rectified to satisfy test coverage requirements. This method will be explained in generic terms to assist the reader in employing the technique in a product design with specific examples given from the implementation of boundary scan in a dense and complex Motorola Cellular Infrastructure board-set. The shift in test method for Motorola from bed-of-nails to Boundary Scan was intensified by the incorporation of a system-level 1149.1 architecture to re-use designed-in product features for postproduction testing.

Board-level boundary scan testing, focusing largely on the boundary scan EXTEST mode for structural testing of interconnects between boundary scan devices on a board and testing of conventional, nonscan components which cannot be accessed using traditional in-circuit or cluster test techniques, is dealt with. Strategies and test-nail placement for implementing various types of boundary scan testing are detailed. The strategies discussed are virtual interconnect, virtual in circuit, standard cluster testing, and virtual cluster testing. It is shown that, where restricted physical access hampers in-circuit or cluster testing, virtual access provided by boundary scan device leads may offer the means of assuring a comprehensive test. When both physical and virtual access is needed, this requirement must be taken into account during board design and factored into board layout to ensure successful implementation of the test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10–20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to non optimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products.

Testing different modules of an integrated circuit concurrently is an efficient way to reduce the total test time. This paper presents a procedure to optimize the parallel test plan to test all functional units present in a data path. Our algorithm defines which registers will be transformed into test pattern generators (TPGs) and signature analyzers SAs, minimizing a test cost function. Our procedure assumes that cellular automata (CAs) registers will be used both for TPG and SA. Each FU's test is defined in terms of: registers to be used as TPGs; registers to be used as SAs; CAs rules to implement TPG and SA; number of test vectors; fault coverage; and test session. Very good results were obtained for the tested architectures. A comparison between the parallel test and a serial test has shown a large test time reduction with a small hardware penalty. This procedure is part of an ongoing research which consists of the development of tools to automatically generate BIST testable circuits along with complete optimized test plans for architectures synthesized by the MACH High-Level Synthesis System.

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.

A test strategy for testing NoC switches based on flooding is presented in this paper. This test strategy tests all switch ports and network routes, while it avoids sending a test packet arriving at a switch in every direction. This test strategy is referred to as pseudo-exhaustive, versus the exhaustive testing that sends an incoming test packet of a switch in every direction. As compared with the exhaustive strategy, the pseudo- exhaustive testing consumes lower power consumption, has a lower test time and still has 100% switch port fault coverage. This paper discusses our test strategy, test mode switch hardware requirements, and evaluates test power, time, and coverage.

Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage can be achieved in a feasible testing time. >

The author describes a system-level built-in test architecture and illustrates how system designers can interface to boundary (and other) scan devices on boards to facilitate line replaceable unit and system-level built-in test, online monitoring, and fault isolation using both serial and real-time techniques. He also shows how to bridge the protocol gaps between the various scan design devices (e.g. LSSD, boundary scan, and VHSIC) to arrive at an integrated built-in test and diagnostics strategy. It is concluded that the only way to achieve the fault detection and fault isolation requirements for the system is to design each card to be fully testable. Each designer could configure the circuit in any way desired and use any mix of components. The only rule is to have testability circuitry that can communicate with a standard testability bus interface on each card so that the system BIT (built-in-test) processor can perform its tasks. >

This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5/spl times/2/sup n/ vectors to the modified circuit under test (CUT), and counting the number of 1's in the output response. The second method uses the same test pattern generator (TPG), but faults are detected by a self comparison technique without the need of storing a signature. Finally, we propose a new adaptive BIST technique, where the TPG is driven by the past outputs of the CUT itself In all the cases, the TPG is universal, i.e., if does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector, nor any fault dictionary, is required. These approaches provide simplicity, less testing time and test data, and compare favorably with earlier BIST designs for CMOS circuits.

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault coverage with a reasonable length of test sequence. Since the correlation between consecutive vectors applied to a circuit during BIST is significantly lower, switching activity in the circuit can be significantly higher during BIST than that during its normal operation. Excessive switching activity during test application can damage CUTs during BIST. The proposed BIST decreases the number of transitions that occur at scan inputs during scan shift operations and hence decreases switching activity during BIST. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST TPG, both of which are proposed in previous publications. This paper shows that the 3-weight WRBIST TPG, which is used to detect random pattern resistant faults, can also be used to reduce switching activity in CUTs during BIST. Experimental results also show that the proposed BIST can be implemented with very low area overhead.

In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive TPG in a two-dimensional TPG architecture. The reduction in hardware overhead is achieved by a new technique that merges the logic of the original TPG mechanism with that of the required phase shifter network in order to yield an improved compact structure.