Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks

The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.

Both wrapper and TAM are important components in SOC test architecture, and wrapper scan chain optimization and TAM optimization are NP-hard problems. Addressing wrapper scan chain optimization or TAM optimization separately leads to SOC test time sub-optimal. This paper presents a TWC&S (TAM/wrapper co-optimization and scheduling) algorithm for multi-clock SOC after combining the advantages of wrapper scan chain optimization and TAM optimization, and it aims to decrease test time of multi-clock SOC extremely. To demonstrate the validity of the proposed algorithm, experiment is performed on the multi-clock SOC MCDS 2 . The results show that there exist inflexion of test time, and the optimal test time is 23.2% when the widths of test bus are 20 vs. the least one. The phenomenon, decreasing degree of test time decreases slowly with test bus widths increase, demonstrates that trade-off will be achieved properly among test time, test area and design complexity.

A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip (SoC) test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC’02 test benchmark.

According to embedded IP core structure and various DFT strategies, it is difficult to test NoC-based SoC especially for reuse situation. The paper proposes the design of a compatible IEEE 1500 standard core test wrapper, which makes different IP cores homogeneous from the point of test integration. A test response comparator is added to the test wrapper, which is capable of verifying directly whether there is failure in this IP. The comparator not only improves testing efficiency and also supports various test modes. The function and timing simulation of proposed wrapper are accomplished on ISCAS '89 circuits. A 2D Mesh NoC was constructed based on these wrappered IP cores and implemented unicast and multicast testing. The experimental results show that the wrapper can effectively realize embedded IP test access and isolation, and has the good adaptability to support various NoC test strategies.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC'02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.

This paper presents a novel approach for selecting optimal pseudo random and deterministic test patterns and minimizing test time for multi-clock domain SoCs based on a hybrid BIST architecture for each core. For test scheduling, a concurrent method considering peak power upper bound is used. A test scheduling graph is presented for modeling concurrent hybrid BIST test scheduling. Furthermore, a heuristic is proposed for selecting cores to be tested concurrently and the order of applying sequence of test patterns to each core. Experimental results show that the proposed heuristics for both selecting groups of cores to be tested concurrently during the SoC test process, and determining the amount of deterministic and pseudo random test patterns for each core, give us an optimized method for multi clock domain SoC testing compared with the existing methods.

Network-on-chip (NoC) has been proposed as a scalable communication infrastructure to establish connections between integrated cores which are increased on a single chip. NoC structure consisting of components and elements such as routers, processing elements and links that can be error prone. Therefore, to achieve the correct functioning of a network, test operation has been a major concern for chip designers. In offline test mechanism, the distance between test pattern generator and destinations has significant impact on the test time. Using multicast scheme, this paper proposed a new mechanism that tests all cores. Our proposed approach first divides the network to four parts and then locates one ATE with four ports in the middle of the network. Based on our method, test operations are manipulated in parallel on each partition, individually. A new method is proposed that distributes test packets and collects test responses, simultaneously. Simulation results were also compared with some prior works by means of the proposed mechanism indicating that delivering test packets’ latency was decreased about 63% and the total number of hop counts to reach the specified destination was declined approximately 34%.

Test scheduling is an important task for the test of a system on chip, and it determines the assignment of cores to the test access mechanism such that the overall test time is minimized. A new test scheduling approach based on cultural algorithms for system on chip is presented in this paper. First of all, the optimization model of test scheduling is given, the model uses the information such as the bits width of the test access mechanism and the scale of test sets of cores, the crosstalk fault test sets of core interconnect lines is also discussed. Secondly, a method based on cultural algorithms is proposed to solve the optimization model of test scheduling. The ant colony algorithm is used in the population space, and the conventional genetic algorithm is used in the belief space. The feasible solutions of test scheduling are represented by individuals, a lot of individuals form the populations. The optimal test scheduling scheme is obtained by the evolution of the populations. Experimental results on a lot of benchmark circuits show that the proposed approach in this paper can solve the problem of test scheduling effectively.

A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testing different modules of an integrated circuit concurrently is an efficient way to reduce the total test time. This paper presents a procedure to optimize the parallel test plan to test all functional units present in a data path. Our algorithm defines which registers will be transformed into test pattern generators (TPGs) and signature analyzers SAs, minimizing a test cost function. Our procedure assumes that cellular automata (CAs) registers will be used both for TPG and SA. Each FU's test is defined in terms of: registers to be used as TPGs; registers to be used as SAs; CAs rules to implement TPG and SA; number of test vectors; fault coverage; and test session. Very good results were obtained for the tested architectures. A comparison between the parallel test and a serial test has shown a large test time reduction with a small hardware penalty. This procedure is part of an ongoing research which consists of the development of tools to automatically generate BIST testable circuits along with complete optimized test plans for architectures synthesized by the MACH High-Level Synthesis System.

Test scheduling for core-based SoCs is a challenging problem. Test schedules must be crafted with the objectives of minimizing testing time and ATE vector memory requirements, to reduce test cost, under the constraints of total available test access mechanism (TAM) width. Prior research in test scheduling has mainly used search procedures like ILP and rectangle packing to solve this problem, but these approaches are inherently computationally expensive. In this paper we describe a novel algorithm to solve the test scheduling problem using a combination of network flow algorithms, malleable job scheduling and reconfigurable wrapper design. Our approximation algorithm has polynomial time complexity and produces schedules close to the theoretical lower bound. Extensive experimental results using the new ITC'02 SoC benchmarks validate the quality of our solutions.

As multiprocessor (or multicore) real-time systems become popular, there has been much research on multiprocessor real-time scheduling algorithms. This work evaluates EDZL (Earliest Deadline until Zero Laxity), a scheduling algorithm for real-time multiprocessor systems. First, we compare the performance of EDZL schedulability tests. We measure and compare the ratio of task sets admitted by each test. We also investigate the dominance between EDZL schedulability tests and discover that the union of the demand-based test and the utilization-based test is an effective combination. Second, we compare the schedulability of EDZL and EDF(k). We prove that the union of the EDZL schedulability tests dominates the EDF(k) schedulability test, i.e., the union of the EDZL schedulability tests can admit all task sets admitted by the EDF(k) schedulability test. We also compare the schedulability of EDZL and EDF(k) through scheduling simulation by measuring the ratio of successfully scheduled task sets. EDZL can successfully schedule 7.0% more task sets than EDF(k).

A test strategy for testing NoC switches based on flooding is presented in this paper. This test strategy tests all switch ports and network routes, while it avoids sending a test packet arriving at a switch in every direction. This test strategy is referred to as pseudo-exhaustive, versus the exhaustive testing that sends an incoming test packet of a switch in every direction. As compared with the exhaustive strategy, the pseudo- exhaustive testing consumes lower power consumption, has a lower test time and still has 100% switch port fault coverage. This paper discusses our test strategy, test mode switch hardware requirements, and evaluates test power, time, and coverage.

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.