Thermal-aware test scheduling using network-on-chip under multiple clock rates

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

Integer Linear Programming (ILP) is commonly used in high level and system level synthesis. It is an NP-Complete problem (in general cases). There exists some tools that give an optimal solution for small ILP formulations. Nevertheless, these tools may not give solutions for complex formulations. In this paper, we present a solution to overcome the problem of complexity in ILP formulations. We propose a partitioning methodology based on a constraint graph representing all the constraints included in any ILP formulation. To direct the partitioning, the constraint graph nodes are grouped to represent Data Flow Graph (DFG) nodes. This reduced constraint graph can be used to partition any ILP formulation based on DFG. We illustrate this method on ILP formulation for scheduling. Results on ILP scheduling formulations are promising.

In this paper we propose new simple integer linear programs (ILPs) formulations for minimizing capacity (in wavelength link) utilization in survivable WDM network. The study examines the performance of shared based protection schemes, such as path protection scheme and link protection scheme under single fiber failure. The numerical results obtained show a reduction in capacity utilization using random traffic compared to the reported ILP formulation. We also present the results using Poisson’s traffic to identify the frequently used links for the widely used NSF network. The proposed work not only reduces the wavelength consumption in different traffic scenarios but also efficient in terms of simulation time. In this paper we propose new simple integer linear programs (ILPs) formulations for minimizing capacity (in wavelength link) utilization in survivable WDM network. The study examines the performance of shared based protection schemes, such as path protection scheme and link protection scheme under single fiber failure. The numerical results obtained show a reduction in capacity utilization using random traffic compared to the reported ILP formulation. We also present the results using Poisson’s traffic to identify the frequently used links for the widely used NSF network. The proposed work not only reduces the wavelength consumption in different traffic scenarios but also efficient in terms of simulation time.

Digital micro fluidic biochips have become one of the most promising technologies in many biomedical fields. In a digital micro fluidic biochip, a group of (adjacent) cells in the micro fluidic array can be configured to work as storage, functional operations, as well as for transporting fluid droplets dynamically. There has been proposed a very efficient Integer Linear Programming (ILP)-based method to schedule operations with considering this dynamic reconfigurability. However, the method cannot directly deal with a case having an operation with multiple successors, which is necessary in some bioassays, e.g., Sample preparation applications. Sample preparation is a crucial preprocessing step to produce droplets of the desired target concentrations from input reagents. In every optimized application graphs for sample preparation, there are many operations with more than one successors. Thus, the previous method cannot be used to get an optimal scheduling, and thus we propose a new framework to use another ILP formulation for scheduling operations in a digital micro fluidic biochips. Our formulation can successfully deal with a case where there is a node with multiple successors. Also, our method can find a binding solution at the same time unlike the above-mentioned previous one thanks to our new ILP formulation. Although our ILP formulation seems to be a bit more complex than the previous one, a preliminary experiment demonstrates that the proposed ILP formulation can successfully find the optimal scheduling for practical sample preparation applications within a reasonable time.

Network-on-chip (NoC) has been proposed as a solution for the interconnection architecture design problem of System-on-chip (SoC) design in nanoscale technologies. NoC architecture for application specific SoC can be optimized by constructing custom topologies that are more suitable for the given application. In nanoscale technologies, the link energy consumption will constitute a considerable part of the total communication energy. Therefore, the total energy consumption of the NoC is strongly influenced by systemlevel floorplan. In this paper, we present a novel integer linear programming( ILP) based technique for joint optimization of NoC with system-level floorplan. We also present a clustering based heuristic technique to reduce the runtime of the ILP formulation. Experimental results with realistic benchmarks applications demonstrate superiority of custom NoC topologies generated by our techniques over mesh based networks, and high quality of the clustering based technique when compared with the ILP formulation.

Recently, a biochip called MEDA (Micro Electrode Dot Array) has been studied in the field of biochemistry. During conducting experiments using a MEDA biochip, we need to move a droplet to a target position. We can split a droplet to make it smaller, and/or change its shape to go through a narrow path on a MEDA biochip. Because the velocity of a droplet is different depending on its shape and the direction of the movement, it should be complex to find an optimal routing for a droplet (i.e., to determine where to split the droplet, which path should be taken, etc.). Thus, existing methods utilize ILP (Integer Linear Programming) formulation to find an optimal routing; existing methods cannot treat large-scale problems because ILP formulation is inherently an exponential algorithm to the problem size. This paper proposes a completely new approach from the ILP formulation; our method constructs a weighted graph so that we can utilize Dijkstra's algorithm to find an optimal routing in polynomial time with respect to the chip size. Our experimental result confirms that the proposed method reduces computation time by more than 99% compared to existing ILP-based methods, and we can now find an optimal routing for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$100 \times 100$</tex>-sized chip, which is totally impossible by existing ILP-based methods.

This paper presents a technique for memory optimization for a class of computations that arises in the field of correlated electronic structure methods such as coupled cluster and configuration interaction methods in quantum chemistry. In this class of computations, loop computations perform a multi-dimensional sum of product of input arrays. There are many different ways to get the same final results that differ in the required number of arithmetic operations required. In addition, for a given number of arithmetic operations, different expressions of the loop have different memory requirements. Loop fusion is a plausible solution for reducing memory usage. By fusing loops between producer loop nest and consumer loop nest, the required storage of intermediate array is reduced by the range of the fused loop. Because resultant loops have to be legal after fusion, some loops can not be fused at the same time. In this paper, we have developed a novel integer linear programming (ILP) formulation that is shown to be highly effective on a number of test cases producing the optimal solutions using very small execution times. The main idea in the ILP formulation is the encoding of legality rules for loop fusion of a special class of loops using logical constraints over binary decision variables and a highly effective approximation of memory usage

Computer architecture is transiting from the multicore era into the heterogeneous era in which heterogeneous architectures use on-chip networks to access shared resources and how a network is configured will likely have a significant impact on overall performance and power consumption. Recently, heterogeneous network on chip (NoC) has been proposed not only to achieve performance comparable to that of the NoCs with buffered routers but also to reduce buffer cost and energy consumption. However, heterogeneous NoC design for heterogeneous GPU-CPU architectures has not been studied in depth. This paper first evaluates the performance and power consumption of a variety of static hot-potato based heterogeneous NoCs with different buffered and bufferless router placements, which is helpful to explore the design space for heterogeneous GPU-CPU interconnection. Then it proposes Unidirectional Flow Control (UFC), a simple credit-based flow control mechanism for heterogeneous NoC in GPU-CPU architectures to control network congestion. UFC can guarantee that there are always unoccupied entries in buffered routers to receive flits coming from adjacent bufferless routers. Our evaluations show that when compared to hot-potato routing, UFC improves performance by an average of 14.1% with energy increased by an average of 5.3% only.

Summary form only given. We present a way to automatically select, within an architectural synthesis tool, the best operand and operator number systems, in order to find the best speed/area tradeoff. This implies the use of different number systems (redundant and non-redundant) for the same design: this is what we call mixed arithmetics. We present an integer linear programming (ILP) formulation to solve a scheduling problem.

In general, multicast routing and wavelength assignment (MC-RWA) can be subdivided in routing and wavelength assignment issues in wavelength-division multiplexing (WDM) mesh networks. Previous studies on WDM multicast have mainly focused on WDM multicast routing. The multicast wavelength assignment problem is studied in this paper. A unicast routing path can be established by a lightpath in an all-optical network. However, in the multicasting case, a multicast routing tree can be established by a single light-tree or several lightpaths, or a combination of several light-trees and lightpaths. We propose a wavelength assignment algorithm for finding an optimal combination of lightpaths and light-trees to construct a newly required multicast session. First of all, two cost functions are given to evaluate the establishing cost for each feasible wavelength, and then find a set of wavelengths that covers all destinations with the minimal cost using Integer Linear Programming (ILP) formulation. We focus on maximizing the total number of users served in a multicast session and the network capacity. The simulation results show that the proposed algorithm can improve system resource utilization and reduce the blocking probability compared with the First-Fit algorithm.

Coarse-grained reconfigurable array (CGRA) overlays can improve dataflow kernel throughput by an order of magnitude over Vivado HLS. This is possible with a combination of carefully floorplanned high-frequency (645-768 MHz) design and a scalable, communication-aware compiler. Our 2D torus CGRA architecture supports versatile processing element (PE) functionality and a configurable number of communication channels to match application demands. Compared to recent FPGA overlays like CGRA-ME's ADRES and HyCUBE implementations, our design operates at 1.8-3.4× faster clock frequency, while scaling to an orders-of-magnitude larger array size of 19×69 on Xilinx Alveo U280. Our communication-aware compiler targets HLS objectives such as initiation interval (II) and minimizes communication cost using an integer linear programming (ILP) formulation. Unlike SDC schedulers in FPGA HLS tools, we treat data movement as a first-class citizen by encoding the space and time resources communication network of the overlay in the ILP formulation. Given the same constraints on operational resources as Vivado HLS, we can retain our target II and achieve up to 9.2× higher frequency. Our ILP scheduler outperforms a PathFinder space-time router implementation in quality of result by up to nearly 2×.

The Fiber Installation Problem (FIP) in Wavelength Division Multiplexing (WDM) optical networks consists in routing a set of lightpaths (all-optical connections) such that the cost of the optical devices necessary to operate the network is minimized. Each of these devices is worth hundreds of thousands of dollars. In consequence, any improvement in the lightpath routing may save millions of dollars for the network operator. All the works in the literature for solving this problem are based on greedy heuristics and genetic algorithms. No information is known on how good are the solutions provided by these heuristics compared to the optimal solution. Besides, no proof that the problem is NP-Hard can be found. In this paper, we prove that FIP is NP-Hard and also present an Integer Linear Programming (ILP) formulation for the problem. In addition, we propose an implementation of the Iterated Local Search (ILS) metaheuristic to solve large instances of the problem. Computational experiments carried out on 21 realistic instances showed that the CPLEX solver running with our ILP formulation was able to solve 11 out of the 21 instances to optimality in less than two minutes. These results also showed that the ILS heuristic has an average optimality gap of 1% on the instances for which the optimal solution is known. For the other instances, the results showed that the proposed heuristic outperforms the best heuristic in the literature by 7%.

The density of integration in a single chip has progressed by use of the deep submicron of VLSI design rule. Systems on a chip (for short, SoCs), i.e., several functional cores being integrated in a single chip, have become the mainstream technology. On the other hand, A Network on a Chip (NoC), i.e., a communication-centric platform, offers an on-chip interconnection network. The NoC is one of the on-chip communication systems. The NoC is used in place of conventional shared bus systems. There are many NoC topologies for connecting cores to each other, such as Mesh, Ring, Spider on, and so on. To evaluate the NoC topologies, a simulation based approach was used for the modeling and analysis of the topologies. However, some properties of the topologies could affect the performance of the NoC systems. This paper describes about the performances of the topologies about the communication aspects by the simulation based approach.

System on a chip (SOC) based on reusable IP core has been widely used in integrated circuit (IC) design and manufacturing. However SOC efficient test is still the bottle-neck issue. Test scheduling can enhance parallel test to minimize test application time at SOC system level. We present a modified differential evolution (MDE) approach to solve the problems of test scheduling and test access mechanism (TAM) partition for system on chips. A new hybrid mutation mechanism based on the probability estimation operator is introduced in the paper for better handling test scheduling, where the first variation coefficient stays the same but the second variation coefficient changes with iterative times. The different evolutionary strategies are adopted to accelerate effectively convergence without loss in population diversity as far as possible. Different mutation operators and evolutionary strategies are combined to get optimal results. The experimental results on ITC'02 SOC benchmarks are encouraging compared with the improved quantum-inspired evolutionary (IQI), genetic algorithm (GA), the integer linear programming formulation (ILP) and heuristic approaches.

The Prize-collecting Scheduling Problem with Deadlines