Interfacing to boundary scan chips for system level BIT

Three ASIC (application-specific integrated circuit) devices recently designed at AT&T incorporate the ANSI/IEEE Std 1149.1-1990 testability features. The test port is used for control of on-chip boundary-scan (BS) and full chip (macrocell and random logic) built-in-self-test (BIST). Presented are a view of the methods used for implementation, novel circuit sharing between BIST and BS, and results related to device area, performance, fault coverage, and testing. The availability of boundary-scan allowed automatic generation of board-level test vectors and allowed board-level printed wire testing without bed-of-nails techniques. By applying BIST tools to the devices after functional design, fault coverage of all of the ASICs was increased to acceptable levels without the significant time and expense of manual vector writing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.

As today's electronics systems increase in complexity, techniques allowing access to "low level" test resources (built-in self-test, boundary scan) are crucial for developing high fault coverage tests. Two IEEE test bus protocol standards have been defined to provide this access at the module (IEEE 1149.5) and device levels (IEEE 1149.1), respectively. This paper discusses the IEEE 1149.5 standard's proposed method for interfacing to the IEEE 1149.1 boundary scan and the issues associated with this interfacing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM. >

Intelligent Magnetic Detection Microsystems (IMDM) are complex microsystems, which are used to obtain the information of motor flux and speed in single-driveway traffic system; the microsystems have to fulfill the task in a harsh environment of field, which would infect the reliability of system. An effective method to ensure maintenance cost and reliability is to integrate efficient built-in-test and monitoring function into IMDM, so testability analysis is introduced in the design of Microsystems. The Microsystems testing-points and diagnostic strategy are reasonably identified, which are beneficial to implement the rapid detection and fault isolation. This paper presents an approach to construct a fault message matrix based on the functional block diagram and signal flow chart of the microsystems. By analyzing the contribution of the testing-points to fault detection and fault isolation, the matrix is resolved step by step, the most necessary testing-points are identified and optimal diagnostic strategy is determined. Thus, the purpose of fault detection and fault isolation is achieved by the use of the fewest testing-points and short time.

This paper describes the use of boundary scan based tests and embedded built in test (BIT) software in the manufacturing defects testing of a 100 MHz, high density, surface mount multi-chip-module, parallel processing computer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This article addresses the issue of improving energy efficiency in the testing of system-on-chip (SoC) semiconductor systems, including heterogeneous computing cores and AI accelerators. An analysis of SoC architecture and existing Design for Testability (DFT) methodologies is presented, considering energy-saving techniques such as clock gating, power gating, and dynamic voltage and frequency scaling (DVFS). A literature review highlights the insufficient development of a comprehensive approach to reducing power consumption specifically during testing procedures. Practical examples, including Qualcomm Snapdragon, Apple A-Series, and Tesla FSD, demonstrate that integrating low-power techniques into DFT can significantly reduce energy consumption (by an average of 20–35%) without compromising test coverage quality. The proposed analysis confirms the effectiveness of combining traditional scan chains, built-in self-test (BIST), and boundary scan with power management mechanisms, contributing to reduced thermal loads and increased reliability of modern SoCs in mass production. The findings presented in this article will be of interest to leading researchers and practicing engineers in the fields of microelectronics, materials science, and energy optimization, aiming to integrate advanced testing methodologies with innovative energy-saving solutions to develop reliable, high-performance, and environmentally sustainable semiconductor systems.

This paper describes a comprehensive off-line system level test strategy developed for several complex high speed, telecom chips. These chips feature a large number of clocks, mixed analog and digital logic and large high speed RAMs. The test strategy was based on the principles of hierarchical test, DFT reuse, BIST and at-speed test, and was implemented using DFT solutions provided by Logic Vision. The paper further specifies the requirements for integration of the DFT solutions within the ASIC vendor's flow. The final DFT implementation which includes scan, at-speed Logic BIST, RAM BIST, PLL BIST, user-defined IEEE 1149.1 TAP and Boundary Scan with fault insertion capability, is presented The system level test architecture focusing on an in-house developed TAP Master is given. Motivation from a cost saving perspective in system SW development and improved system quality monitoring are highlighted as major driving forces in support of this strategy. Finally, some practical issues for consideration when planning system test based on BIST are presented.

Board-level boundary scan testing, focusing largely on the boundary scan EXTEST mode for structural testing of interconnects between boundary scan devices on a board and testing of conventional, nonscan components which cannot be accessed using traditional in-circuit or cluster test techniques, is dealt with. Strategies and test-nail placement for implementing various types of boundary scan testing are detailed. The strategies discussed are virtual interconnect, virtual in circuit, standard cluster testing, and virtual cluster testing. It is shown that, where restricted physical access hampers in-circuit or cluster testing, virtual access provided by boundary scan device leads may offer the means of assuring a comprehensive test. When both physical and virtual access is needed, this requirement must be taken into account during board design and factored into board layout to ensure successful implementation of the test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagating test responses from the core outputs. In this paper, we present a design for testability and symbolic test generation technique for testing such core-based systems on a chip. The proposed method consists of two parts: (i) core-level DFT to make each core testable and transparent, the latter needed to propagate test data through the cores, and (ii) system-level DFT and test generation to ensure the justification and propagation of the precomputed test sequences and test responses of the core. Since the hierarchical testability analysis technique used to tackle the above problem is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a by-product of the testability analysis and insertion method without further search. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated on two example systems: (i) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan, and (ii) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

Fault detection isolation and diagnosis of multi-axle speed sensors for high-speed trains

Novel Built-In Self-Test (BIST) approaches for integrated optoelectronic systems are presented The methods are compatible with scan chain design and allow testing the internal functionality of the device, the interconnection between modules, the analog characteristics of the transmitters and receivers and the Bit Error Rate (BER) of the channels. The proposed approaches enable system evaluation under realistic operating conditions (including crosstalk degradation) through BER testing. They can speedup both circuit-level and system-level testing by providing means for accessing different parts of the circuit easily and allowing time-consuming performance tests to be run in parallel with boundary-scan tests. Some preliminary experimental results are presented to confirm the proposed approaches for analog and mixed-signal methods.

Actuator health monitoring of military systems is currently performed both on-board the aircraft (at the operational-level) and at ground-based maintenance installations (i.e., intermediate or depot levels). Current onboard health monitoring employs built-in-tests (BITs), which apply conservative thresholds to flight control data to identify problems early and avoid in-flight failures. However, the extreme operation and interdependent nature of these military systems often cause flight control parameters to exceed these thresholds even though the component is healthy. Intermediate or depot testing may fail to recreate the in-flight problems experienced or not substantiate the on-board assessment. This has led to high incidences of can not duplicate (CND) errors, high sparing requirements, and has affected maintenance costs and operational readiness. The authors are developing a control actuator health management (CAHM/spl trade/) software package that employs both data-driven and model-based algorithms to provide diagnostic and prognostic indicators for hydraulic servovalves and mechanical actuators. These software modules use actuator command/response data, physical actuator models, signal processing techniques, neural network modeling, advanced feature and knowledge fusion strategies, classification algorithms, and an evolving array of prognostics methods. Advanced reasoners are also being developed to interpret BIT results for better fault isolation. Each class of diagnostic algorithm has specific requirements and advantages, including the low computational burden of data-driven algorithms (when compared with other diagnostic techniques) and the ability of model-based algorithms to relate faults back to physically meaningful parameters. These diagnostic algorithms will not only help isolate faults, but will also provide a gray-scale health assessment of components, which will be much more useful to maintenance technicians than a simple pass/fail BIT designation. In the presence of sufficient historical health information, diagnosis can be extended to prognosis using a suite of trending algorithms and novel tracking methods to provide an estimate of remaining useful life (RUL). This paper highlights the current state of the innovative software tool, which is initially targeted toward implementation in an intermediate test data environment.

Reliability evaluation of Fault Tolerant Control Systems with a semi-Markov FDI model

A built-in self-test (BIST) approach is presented for the logic resources in the programmable input/output (I/O) tiles in Virtex-5 field programmable gate arrays (FPGAs). A total of 15 BIST configurations were developed to test the I/O cell programmable logic resources in all modes of operation. The approach utilizes dedicated I/O buffer bypass routing in the I/O tile such that the BIST is package independent and applicable to all levels of testing from wafer-level to system-level. The approach offers control of BIST execution and maximal diagnostic resolution of faulty I/O tiles for device and package independent testing. Either the boundary scan interface or a simple system-level interface may be used for BIST execution, control, and diagnosis independent of the configuration interface. Experimental results are presented including fault detection capabilities.