Manufacturing defects testing of a multi-chip-module using IEEE 1149.1 boundary scan test and embedded built-in test software

The author describes a system-level built-in test architecture and illustrates how system designers can interface to boundary (and other) scan devices on boards to facilitate line replaceable unit and system-level built-in test, online monitoring, and fault isolation using both serial and real-time techniques. He also shows how to bridge the protocol gaps between the various scan design devices (e.g. LSSD, boundary scan, and VHSIC) to arrive at an integrated built-in test and diagnostics strategy. It is concluded that the only way to achieve the fault detection and fault isolation requirements for the system is to design each card to be fully testable. Each designer could configure the circuit in any way desired and use any mix of components. The only rule is to have testability circuitry that can communicate with a standard testability bus interface on each card so that the system BIT (built-in-test) processor can perform its tasks. >

Board-level boundary scan testing, focusing largely on the boundary scan EXTEST mode for structural testing of interconnects between boundary scan devices on a board and testing of conventional, nonscan components which cannot be accessed using traditional in-circuit or cluster test techniques, is dealt with. Strategies and test-nail placement for implementing various types of boundary scan testing are detailed. The strategies discussed are virtual interconnect, virtual in circuit, standard cluster testing, and virtual cluster testing. It is shown that, where restricted physical access hampers in-circuit or cluster testing, virtual access provided by boundary scan device leads may offer the means of assuring a comprehensive test. When both physical and virtual access is needed, this requirement must be taken into account during board design and factored into board layout to ensure successful implementation of the test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Poor system reliability, combined with frequent failures of Built-In Test (BIT), may cause crew to undertake missions with undetected faults. Further, the need for rapid field repair, combined with line-replaceable unit (LRU) endemic fault isolation, dictates a new approach to system test. The use of JTAG-based boundary-scan test (BST), embedded on-board without the need for external physical hardware probes, cabling and fixturing, is described to address this issue. This paper details the application of JTAG for BIT, Test Access Port (TAP) controller firmware requirements, BST library Application Program Interface (API), and hardware design requirements.

Design for Testability (DFT) provides for economic benefits and reduction in costs for design, manufacturing and support of electronic systems. The amalgamation of increased benefits and net reduced costs is value enjoyed throughout the life cycle of the system. While a number of formulas have been developed over the years to justify DFT, a unifying methodology is needed that can be used to calculate the overall economic value of DFT. The methodology we use in this paper relates known input benefit and cost parameters and map their dependencies to higher level DFT benefits and costs. This method demonstrates the numerous ways DFT can improve a system's life cycle value. It can also be used to justify the costs of DFT, such as added engineering labor, additional parts, higher cost boundary scan and built-in self test (BIST) parts. Moreover, they help convince financially focused management that DFT is a worthwhile investment even though the expenditures are in the early part of the life cycle and the return on that investment may be years later. Proponents of DFT need the methodology we present here to back up their assertions that DFT is profitable. Using dependencies lends itself to programming and calculations of DFT value can be readily performed by spreadsheet programs.

Three ASIC (application-specific integrated circuit) devices recently designed at AT&T incorporate the ANSI/IEEE Std 1149.1-1990 testability features. The test port is used for control of on-chip boundary-scan (BS) and full chip (macrocell and random logic) built-in-self-test (BIST). Presented are a view of the methods used for implementation, novel circuit sharing between BIST and BS, and results related to device area, performance, fault coverage, and testing. The availability of boundary-scan allowed automatic generation of board-level test vectors and allowed board-level printed wire testing without bed-of-nails techniques. By applying BIST tools to the devices after functional design, fault coverage of all of the ASICs was increased to acceptable levels without the significant time and expense of manual vector writing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Novel Built-In Self-Test (BIST) approaches for integrated optoelectronic systems are presented The methods are compatible with scan chain design and allow testing the internal functionality of the device, the interconnection between modules, the analog characteristics of the transmitters and receivers and the Bit Error Rate (BER) of the channels. The proposed approaches enable system evaluation under realistic operating conditions (including crosstalk degradation) through BER testing. They can speedup both circuit-level and system-level testing by providing means for accessing different parts of the circuit easily and allowing time-consuming performance tests to be run in parallel with boundary-scan tests. Some preliminary experimental results are presented to confirm the proposed approaches for analog and mixed-signal methods.

A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Embedded built-in test (BIT) software typically provides a system-level go/no-go indication and, in the presence of a failure, may provide some level of sub-system isolation. This level of reporting, while meeting the customer's operational requirements, does little to support system integration, production, and repair. To support these other needs, "instrumentation code" is added to the BIT software to provide detailed test data through an external interface. Since the BIT software already accesses the hardware parameters for testing, it becomes the most logical component for the instrumentation. This paper describes the techniques of embedding instrumentation during BIT design and development to support a broad range of program test needs. It explains the costs and benefits associated with the use of instrumentation. It gives specific examples of instrumented software and describes how instrumentation data can be used during environmental tests, factory test, and depot test. The impact instrumentation has on software development time, code size, execution time, and reliability is discussed as well as the cost of retrofitting BIT software to add instrumentation. Some of the benefits as well as the challenges to developing effective embedded instrumentation is also examined.

As today's electronics systems increase in complexity, techniques allowing access to "low level" test resources (built-in self-test, boundary scan) are crucial for developing high fault coverage tests. Two IEEE test bus protocol standards have been defined to provide this access at the module (IEEE 1149.5) and device levels (IEEE 1149.1), respectively. This paper discusses the IEEE 1149.5 standard's proposed method for interfacing to the IEEE 1149.1 boundary scan and the issues associated with this interfacing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An important activity in component-based software development is the testing of each component in its context of use. Since a component developer cannot anticipate all possible applications of the component, this task is usually left to the component user. What makes testing of component-based software especially challenging for the user is the lack of source code and partial knowledge of the working of the component. To ensure high quality of the overall software, the component user must perform testing tasks, i.e., generate test cases, create test oracles, evaluate coverage, and perform regression testing, all without access to the component’s source code or complete semantic knowledge. The developer of the component can facilitate the execution of these testing tasks by augmenting the component appropriately with information that improves its testability. This chapter describes techniques that can be employed by developers to build testable COTS components. A taxonomy of these techniques based on the phases of software testing and the role of the component developer/user is presented, followed by a description of an important subset of the following techniques: (1) State Machine Models, (2) Built-In Tests, (3) Built-In Contract Testing, (4) Interface Probing, (5) Traceable Components, (6) Metacontent, (7) Binary Reverse Engineering, (8) Fault Injection Support, (9) Testable Beans, (10) Retro Components, (11) Component Test Bench, and (12) Self-Testing Components. Finally, a discussion summing up all the techniques is presented.

A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM. >

With the fast development of electronic industry,the techniques of testing electronical system have varied from traditional functional test to structured test accordingly.The principel of functional test is presented in this paper and the representative techniques of structured test, as in-circuit test(ICT),boundary-scan test(BST),build-in self-test(BIST) and scan-path test,are explored subsequently.Finally,the developmenting trends in the future are looked forward to.

This article discusses the development of a board level manufacturing test for a surface mount board implemented with boundary scan. The board examined is a composite of several actual products. Methods for effectively developing a boundary scan test are examined along with some of the advantages of approaching the development in unique ways. Additionally, the criteria for using these methods are developed. Results for test development time and the resulting test coverage show that with two weeks of test development using boundary scan it is possible to increase the rate of solder opens detection from 80% to 99% for a large ball-grid-array module.

Parallel dynamic process simulation of a distillation column on the BBN Butterfly Parallel Processor computer

This article addresses the issue of improving energy efficiency in the testing of system-on-chip (SoC) semiconductor systems, including heterogeneous computing cores and AI accelerators. An analysis of SoC architecture and existing Design for Testability (DFT) methodologies is presented, considering energy-saving techniques such as clock gating, power gating, and dynamic voltage and frequency scaling (DVFS). A literature review highlights the insufficient development of a comprehensive approach to reducing power consumption specifically during testing procedures. Practical examples, including Qualcomm Snapdragon, Apple A-Series, and Tesla FSD, demonstrate that integrating low-power techniques into DFT can significantly reduce energy consumption (by an average of 20–35%) without compromising test coverage quality. The proposed analysis confirms the effectiveness of combining traditional scan chains, built-in self-test (BIST), and boundary scan with power management mechanisms, contributing to reduced thermal loads and increased reliability of modern SoCs in mass production. The findings presented in this article will be of interest to leading researchers and practicing engineers in the fields of microelectronics, materials science, and energy optimization, aiming to integrate advanced testing methodologies with innovative energy-saving solutions to develop reliable, high-performance, and environmentally sustainable semiconductor systems.