Optical communication channel test using BIST approaches

Built-in self-test (BIST) approaches are suitable for in-field testing since they do not require a tester for storage and application of test data. They also reduce the security vulnerabilities associated with loading and unloading of external test data into scan chains. As technologies evolve, in-field testing needs to address more complex defect and aging mechanisms that require specific deterministic tests. This can be addressed by BIST approaches that store test data on-chip and use the data for on-chip generation of both random and deterministic tests. In this case, there is a tradeoff between the amount of stored test data and the comprehensiveness of the test set that can be applied. This article explores this tradeoff in a specific context that has the following main features: 1) the initial stored test data is based on a stuck-at test set; 2) the target faults are single-cycle gate-exhaustive faults; and 3) the stored test data is enhanced gradually by test data based on a gate-exhaustive test set to increase the coverage of gate-exhaustive faults.

The quality of a digital communication interface can be characterized by its bit error rate (BER) performance. To ensure the quality of the manufactured interface, it is critical to quickly and precisely test its BER behavior. Traditionally, BER is evaluated using software simulations, which are very time-consuming. Though there are some standalone BER test products, they are expensive and none of them includes channel emulators, which are essential to testing BER under the presence of noise. To overcome these problems, we present a versatile scheme for BER testing in FPGAs. This scheme consists of two intellectual property (IP) cores: the BER tester (BERT) core and the additive white Gaussian noise (AWGN) generator core. We demonstrate through case studies that the proposed solution exhibits advantages in speed and cost over existing solutions.

This rsearch work presents an educational software interface tool for analyzing and estimating the bit error rate (BER) of an optical communication system. Currently BER estimation tool required expensive measurement equipment such as serial data analyzer (SDA) and BER Tester. In addition to cost all this equipment is also limited to BER estimation based on standard format and is not suitable for custom analysis because of time constraint to use equipment even during offline estimation. This educational software interface tool is developed using OPTISYSTEM software and built-in MATLAB command. MATLAB GUI is used as the software tool because it’s friendly user. OPTISYSTEM is used to design the PAM two levels, four levels, and eight levels system. MATLAB is used as an interface to build the BER estimation tool for measuring the PAM multilevel modulation technique. The MATLAB GUI system for measuring BER is design using Gaussian probability errors approximation method. The designed BER estimation tool simulation, is able to plot the eye diagram, BER diagram, Q-factor value, threshold value, and the most important function is to analysis the BER value for two levels, four levels and eight levels of a PAM optical communication systems.

We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.

Wireless Digital Laser Communication Link (WDLCL) is an emerging technology and alternate to the conventional RF / Fiber link with numerous advantages / applications. The data link quality can be best estimated by measuring the Bit Error Rate (BER) in WDLCL. Since the characteristics of WDLCL severely affected by the atmosphere, an experimental based study about the turbulence medium becomes significant. In this paper, the complete theoretical concepts related to the challenges of WDLCL are listed. The Opto-electronic architecture (Tx and Rx) developed in this research is detailed with the necessary photographs. The core design of the low-cost BER Tester (BERT) is developed in the reconfigurable Field Programmable Gate Array (FPGA) is explained. The BER is measured in various atmospheric conditions for different beam radius and link distance and the observations are reported. Over a long period of time, real-time experimental data was continuously collected and the results were analyzed. Beam scintillation, spreading and wandering were accounted as the atmospheric turbulent effects on the laser beam with beam steering system. The experimental results reveal that atmospheric turbulence has a significant impact on the BER.

A description is given of the design of a broadband downconverter to cover both 4-GHz and 6-GHz common carrier bands. The downconverter was tested as a replacement for the downconverter in both the MDR-2204 and MDR-2306 4-GHz and 6-GHz radio systems, respectively. Excellent results have been observed in both radio systems. In threshold bit error rate (BER) tests, the downconverter provided 1.2-dB better performance than both radio systems. In overload BER tests, the downconverter showed a 0.5-dB better performance. The features credited for the good performance are: (1) the noise figure of the low-noise amplifier is less than 1.7 dB over the band; (2) the phase noise of the local oscillator is quite low; (3) the two-tone third-order intercept point of the downconverter is above 26 dBm; and (4) the image rejection is greater than 20 dB over the band. >

The COPERNICUS project UBISTA (Unified Built In SelfTest Approach) has considered techniques to allow a digital signature to be produced from the analogue transient thus allowing the complete mixed signal device to be tested using standard digital test equipment. It is with an example of such data compression this paper is concerned.

The added benefits brought by the advent of the Vehicular network (VN) technology have stimulated a lot of hope in the area emergent transportation industries. Two most important factors that have motivated and contributed to the development, design and implementation of the VN standards include the need to ensure safety and the need to consider road accident avoidance strategies. However, the innate dynamic and the high topological mobility of the nodes in Vehicular Ad Hoc Networks (VANETs) raise complex and challenging issues with the standard. One of the complexities is the problem posed by Doppler effect (DE) resulting from the high mobility of the VANET nodes. In an attempt to compensate the induced Doppler shift (DS), the Automatic Doppler shift adaptation (ADSA) method was recently introduced to combat DE in a VANET. ADSA proved to be more resilient and effective in term of Bit error rate (BER). Moreover, for realistic applications, BER tests alone are insufficient. Therefore, in this work, a thorough analysis of the method is explored and the strength of the refined ADSA method is evaluated in terms of throughput, elapsed time, packet loss, model efficiency and data transfer rate. These metrics are used to perform a comparative analysis of ADSA versus adaptive modulation code (AMC) and auto-rate fallback (ARF). Results from the analysis shows that the ADSA approach is very effective and has a strong robustness compared to ARF and AMC with up to 300–700 % improvement in throughput and a 60–75 % reduction in consumed time.

Operating frequencies of combinational logic circuits can be increased using Wave-Pipelining (WP), by adjusting the clock periods and clock skews. In this article, Built-In Self-Test (BIST) and System-on-Chip (SOC) approaches are proposed for automating this adjustment and they are evaluated by implementation of filters using a Distributed Arithmetic Algorithm (DAA) and sinewave generator using the COordinate Rotation DIgital Computer (CORDIC). Both the circuits are studied by adopting three schemes: wave-pipelining, pipelining, and nonpipelining. Xilinx Spartan II and Altera Cyclone II FPGAs with Nios II soft-core processor are used for implementation of the circuits with the BIST and SOC approaches, respectively. The proposed schemes increase the speed of the WP circuits by a factor of 1.19--2.6 compared to nonpipelined circuits. The pipelined circuits achieve higher speed than the WP circuits by a factor of 1.13--3.27 at the cost of increase in area and power. When both pipelined and WP circuits are operated at the same frequency, the former dissipates more power for circuits with higher word sizes and for moderate logic depths. The observation regarding the dependence of the superiority of the WP circuits with regard to power dissipation on the logic depth is one of the major contributions of this article.

The Aim is to Implement RTL Design Architecture for Compatible Serial Bit Error Rate Tester SOCa Multi rate Multichannel PRBS Sequence Based SERIAL BERT IP Core for High Speed Wireless Serial Communication Data Acquisition SOC Transceiver Products a Applications (3G, 4G, GPS, GSM, CDMA, WIFI, GIFI etc). Testing of Data Done By Different PRBS Pattern Sequences-2e7-1, 2e10-1, 2e15-1, 2e23-1, 2e31-1. Basically this Serial BERT Consists of PRBS Generator Module located in the Transmitter Side a sends Pseudo Random Pulse signal is transmitted by the Serial link. Second Module is located in the receiver generate the same signal a compare with the transmitted signal, if any errors, like bit slip, bit error, Additive white Gaussian noise (AWGN), can then be detect the number of errors, and these errors are evaluated by the BERT core, estimate the error rate w.r.t number of bits. Design implementation through Soft Process Description using VHDL a Verilog HDL, Simulation a Synthesis of design done by Xilinx ISE Software Design Tool, Testing a Debugging done by FPGA Spartan Development Kit.

In the RF and mixed signal IC design, Built in Self Test (BIST) technique is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. In most cases, these systems are evaluated and designed with electrical stimulation method. The main problem of electrical simulation tools is that the extraction of the parameters associated with the performances of circuit and the design rules depend broadly on the intuition of the experts. To overcome this problem, an efficient methodology for top-down design, modeling, and simulation of complete BIST circuit to validate its proper function before moving on to transistor level implementation is presented in this paper. The described method is based in behavioral modeling strategy using hardware description language VHDL-AMS. At behavioral level, the performances of circuits are optimized by modeling and simulation these performances parameters with a hardware description language without considering its transistor level implementation. Hence, methods and algorithms for modeling has been developed, for simulation, in order to decrease the total simulation time, validation of systems, and accelerate the production cycle of electronic devices. The proposed BIST schema based on modeling and simulation strategy is applied to test a loop filter. Extensive simulation study shows that the proposed BIST approach can efficiently detect the loop filter fault and tolerate this type of fault, and so offers high fault coverage of 100% for the fault detects.

Poor system reliability, combined with frequent failures of Built-In Test (BIT), may cause crew to undertake missions with undetected faults. Further, the need for rapid field repair, combined with line-replaceable unit (LRU) endemic fault isolation, dictates a new approach to system test. The use of JTAG-based boundary-scan test (BST), embedded on-board without the need for external physical hardware probes, cabling and fixturing, is described to address this issue. This paper details the application of JTAG for BIT, Test Access Port (TAP) controller firmware requirements, BST library Application Program Interface (API), and hardware design requirements.

In this research work, we have developed a communication system (transmitter / receiver) to control peak to average power (PAPR) with small bit error rate (BER) for a 4G system called multicode code division multiple access (MCCDMA). Proposed communication system works on modified Reed Muller encoded data (MRMED) string. In MRMED data is first encoded with Reed Muller (RM) code. Thereafter, encoded RM message is XORed with optimal binary string, which results lower Peak to Average Power ratio (PAPR). A well-known fact is that, bit error rate (BER) is the best performance measurement tool for a communication system. To check the integrity of our communication system, we have run the simulation for monitoring BER using MRMED sequence. Simulation work conducted, with multipath Rayleigh fading, Minimum Shift Keying (MSK) modulation and several orders of RM codes. Our results show that implementing MRMED sequences of the suggested MCCDMA communication structure, returns noticeable lower BER. For instance, in case of RM(1,4), that has error improvement proficiency of 3 (three) errors , returns BER = 8.2x10−5 adopting MSK, at SNR = 12dB. Similarly, for RM(2,3), which has error improvement efficiency of 0 error and shows distinct BER of 4.9x10−4 at 12dB (SNR).In addition to using simulation for checking BER performance of our communication system, we have also shown in our results that, as the error improvement capability of different RM codes surges, correspondingly we get a lower BER.

Numerous Built-In Self Testing (BIST) designs now exist for the testing of Programmable Logic Arrays (PLA), but their practical usefulness has not been studied. In this paper, we implement and compare several BIST designs using a common methodology of implementation. We also perform an yield analysis to characterize the yield degradation due to the BIST design methodology. Our preliminary findings of this work is that BIST approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for PLAs.

The increasing demand for high-density and high-speed digital optical recording systems has made the development of advanced coding and signal processing techniques for fast and reliable data recovery increasingly important. In recent years, the parity-check (PC)-code-based reception technique has been widely studied for magnetic recording systems, and it is projected to be highly promising for high-density optical recording. The PC code is an inner error correction code (ECC), which can detect dominant short error events of the system, using only a few parity bits. This reduces the loss in error correction capability of the outer ECC due to random short errors and results in a simple and efficient solution to improve the overall performance. This thesis is dedicated to the design and analysis of PCcode- based recording systems to achieve higher recording capacity with low implementation complexity, for high-density blue laser disc systems. In particular, most of the key components of the PC-code-based optical recording system have been designed and optimized for different recording densities, and different proportions of white noise and media noise. During the development of advanced coding and detection techniques, it becomes necessary to investigate the system’s performance with different coding schemes and recording densities. In Chapter 2 of the thesis, we propose a generalized Braat-Hopkins model for optical recording channels, which provides a fair basis for the performance comparison of detection schemes over different coding schemes and recording densities, for channels with additive, white Gaussian noise (AWGN) and media noise. Various basic issues associated with the PC-code-based systems are investigated in Chapter 3. These include bounds for bit error rates and error event probabilities, the dominant error events at channel detector output, different PC codes, simple and efficient post-processors, the impact of error events that are split across data block boundaries and the corresponding remedy, as well as the effects of code rates and recording densities. Simulation results show that a 4-bit PC code achieves the best performance. The corresponding bit error rates (BERs) are very close to the performance bounds, at both nominal and high densities. Constrained codes, which serve as a key component in the read-write channel of data storage systems, are desired to have a high code rate with low-complexity encoder/decoder. In Chapter 4, we investigate the design of certain capacity-approaching constrained codes for optical recording systems. In particular, we derive analytically the relationship between the number of encoder states and the maximum size of these codes. We identify the minimum number of encoder states that maximizes the code rate, for any desired codeword length. The design of constrained PC codes is key to the development of PCcode- based systems, and the systematic design of efficient constrained PC codes remains a challenging problem. In Chapter 5, we propose a general and systematic code design technique for constructing capacity-approaching constrained PC codes, which can detect any type of error events of the system, with the minimum code rate loss. Compared to the rate 2/3 code without parity, the newly designed constrained 4-bit PC code achieves a performance gain of 2 dB at nominal density, and 1.5 dB at high density, at BER = 10-5. As the dominant noise for high-density optical recording systems, media noise severely degrades the performance of channel detectors and postprocessors that are designed for AWGN. In Chapter 6, we propose two novel modifications to the bit detector to combat media noise. We further develop a data-dependent post-processing scheme for error correction. Compared to the system designed without considering media noise and without PC codes, the overall performance gain of the developed scheme can be more than 11 dB at high media noise levels. In data storage systems, the ECC failure rate (EFR) serves as the ultimate measure of the data recovery performance. In Chapter 7, we develop semi-analytical approaches for estimating the EFR, and analyze EFRs for the developed PC-code-based systems, for the cases without and with interleaving. Our analysis shows that with the optimum interleaving degrees, compared to the rate 9/13 code without parity, the 2-bit PC code achieves a gain of around 0.5 dB, and the 4-bit PC code gains 0.6 dB, at high record ing density and EFR = 10-16. The thesis concludes in Chapter 8 with some suggestions for further work.