Coordinated resource optimization in behavioral synthesis

This paper describes an intermediate representation for behavioral and structural designs that is based on annotated state tables. It facilitates user control of the synthesis process by allowing specification of partially design structures, and a mixture of behavior, structure and user specified bindings between the abstract behavior and the structure. The format's general model allows the capture of synchronous and asynchronous behavior, and permits hierarchical descriptions with concurrency. The format is easily translated to VHDL for simulation at each stage of the design process. It therefore complements a good simulation language (VHDL) by providing an excellent input path for behavioral and register-transfer synthesis. The format's simple and uniform syntax allows it to be used both as an intermediate exchange format for various behavioral synthesis tools, and as a graphical tabular interface for the user, thereby allowing a natural medium for automatic or manual refinement of the design.

Prolonged periods of sedentary behavior are linked to cardiometabolic disease independent of exercise and physical activity. This study examined the effects of posture by comparing one day of sitting (14.4 ± 0.3 h) to one day of standing (12.2 ± 0.1 h) on postprandial metabolism the following day. Eighteen subjects (9 men, 9 women; 24 ± 1 y) completed two trials (sit or stand) in a crossover design. The day after prolonged sitting or standing the subjects completed a postprandial high fat/glucose tolerance test, during which blood and expired gas was collected immediately before and hourly for 6 h after the ingestion of the test meal. Indirect calorimetry was used to measure substrate oxidation while plasma samples were analyzed for triglyceride, glucose, and insulin concentrations. Standing resulted in a lower fasting plasma triglyceride concentration (p = 0.021) which was primarily responsible for an 11.3% reduction in total area under the curve (p = 0.022) compared to sitting. However, no difference between trials in incremental area under the curve for plasma triglycerides was detected (p>0.05). There were no differences in substrate oxidation, plasma glucose concentration, or plasma insulin concentration (all p>0.05). These data demonstrate that 12 h of standing compared to 14 h of sitting has a small effect the next day by lowering fasting plasma triglyceride concentration, and this contributed to a 11.3% reduction in postprandial plasma triglyceride total area under the curve (p = 0.022) compared to sitting.

This paper analyses the register requirements of software pipelined inner loops. When the number of functional units and/or the number of stages of individual functional units is increased, the number of registers required may be prohibitive in chip area and cycle time. We characterize lifetime of values in pipelined loops with their loop register locality (LRL). Based on this characteristic, we propose a new organization of the register file in order not to affect cycle time and also reduce area, while increasing the number of registers. This can be useful to minimize the frequency of spill at a reasonable cost. The spill code can increase the minimum initiation interval and decrease loop performance. This new organization consists of a small high bandwidth multiported register file and a low bandwidth port-limited register file called sack. A mechanism to assign values to the sack is presented. We demonstrate the effectiveness of our approach by experimenting with a collection of loops from the Perfect Club benchmark suite. Experiments in order to find the optimal number of registers into the sack have been done. We also measured the effect of the spill code on loop performance.

Implementation of a FFT processor using pipelining and folding techniques which is achieved by reducing number of functional units, registers and multiplexers. The pipelining and parallel processing techniques deals with the reducing the critical path which in turns increases the speed of the processor, in order achieve high speed, special kind of multipliers and adders are used. The folding transformation is used to systematically determine the control circuits in DSP architectures where multiple algorithm operations (such as addition operations) are time multiplexed to a single functional unit. By executing multiple algorithm operations on a single function unit, the number of functional units in the implementation is reduced resulting in an integrated circuit with low silicon area.

With the development of fabrication, the capacities of application-specific integrated circuits (ASICs) that implement data-intensive applications are increasing as well. in high-level view, the results of functional units (FUs) and register allocation have a significant impact on power, thermal, area and timing etc., especially for data-dominated behaviors. Techniques for power minimization might be applied in different levels of the design hierarchy, but high-level synthesis (HLS) has attracted a special attention due to its inherent ability of better design space exploration. All kinds of methods for register optimization are presented in the recent past. This paper presents a new simultaneous FUs and register allocation method, which combining heuristic list scheduling algorithm and left-edge algorithm to optimize register number and power. From the experimental results, it shows that different FUs allocation results deliver an average 1.83 reduction in register number. And compared with traditional allocation method, we can obtain a 5.81% reduction in power consumption. In order to optimize area with the design demand, it will be at the expense of power dissipation, our design method also can achieve power-area balance.

This paper proposes a novel behavioral synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional units (e.g. multiply-accumulator) are designed for specific operation patterns to achieve shorter delay and/or smaller area than cascaded basic functional units. Almost all conventional methods cannot use specialized functional units effectively under a total area constraint because of their less flexibility for resource sharing. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems utilizing specialized functional units in practical time with some heuristics, and to reduce the number of clock cycles under total area and clock cycle time constraints. Experimental results show that the proposed method has achieved up to 35% and on average 14% reduction of the number of cycles with specialized functional units in practical time.

This paper proposes a novel behavioral synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional units (e.g. multiply-accumulator) are designed for specific operation patterns to achieve shorter delay and/or smaller area than cascaded basic functional units. Almost all conventional methods cannot use specialized functional units effectively under a total area constraint because of their less flexibility for resource sharing. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems utilizing specialized functional units in practical time with some heuristics, and to reduce the number of clock cycles under total area and clock cycle time constraints. Experimental results show that the proposed method has achieved up to 35% and on average 14% reduction of the number of cycles with specialized functional units in practical time.

Speculative Functional Units (SFUs) enable a new execution paradigm for High Level Synthesis (HLS). SFUs are arithmetic functional units that operate using a predictor for the carry signal, which reduces the critical path delay. The performance of these units is determined by the success in the prediction of the carry value, i.e. the hit rate of the prediction. Hence SFUs reduce critical path at a low cost, but they cannot be used in HLS with the current techniques. In order to use them, it is necessary to include hardware support to recover from mispredictions of the carry signals. In this paper, we present techniques for designing a datapath controller for seamless deployment of SFUs in HLS. We have developed two techniques for this goal. The first approach stops the execution of the entire datapath for each misprediction and resumes execution once the correct value of the carry is known. The second approach decouples the functional unit suffering from the misprediction from the rest of the datapath. Hence, it allows the rest of the SFUs to carry on execution and be at different scheduling states at different times. Experiments show that it is possible to reduce execution time by as much as 38% and by 33% on average.

Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools. Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It improves the throughput and reduces the latency of the synthesized hardware. It is complex and error-prone, and a small bug can result in faulty hardware with expensive ramifications. Therefore, it is critical to certify the loop pipelining transformation so that designers can trust the behaviorally synthesized pipelined designs. Certifying a loop pipelining transformation is however, a major research challenge because there is a huge semantic gap between the input sequential design and the output pipelined implementation, making it infeasible to verify their equivalence with automated sequential equivalence checking (SEC) techniques. Complex loop pipelining transformations can be certified by a combination of theorem proving and SEC: (1) creating a certified pipelining algorithm which generates a reference pipeline model by exploiting pipeline generation information from the synthesis flow (e.g. the iteration interval of a generated pipeline) and (2) conduct SEC between the synthesized pipeline and this reference model. However, a key and arguably, the most complex component of this approach is the development of a formal, mechanically verifiable loop pipelining algorithm. We show how to systematically construct such an algorithm, and carry out its verification using the ACL2 theorem prover. We propose a framework of certified pipelining primitives which are essential for designing pipelining algorithms. Using our framework, we build a certified loop pipelining algorithm. We also propose a key invariant in certifying this algorithm, which links sequential loops with their pipelined counterparts. This is unlike other invariants that have been used in proofs of microprocessor pipelines so far. This dissertation provides a framework for creating certified pipelining algorithms utilizing a mechanical theorem prover. Using this framework, we have developed a certified loop pipelining algorithm. This certified algorithm is essential in the overall approach to certify behaviorally synthesized pipelined designs. We demonstrate the

Behavioral synthesis is the task of refining a behavioral description into a Register Transfer Level (RTL) description through a set of successive transformations. The two main models used during this refinement process are the internal representation of the behavioral description, and the target architecture. The internal representation, also called intermediate form, fixes the underlying design model of the behavioral synthesis tool (see CFG, DFG or CDFG further). The choice of this model constitutes one of the main decisions when building a behavioral synthesis tool. Although intermediate forms are generally not accessible to the users of such tools, their understanding may help to better comprehend the functioning of the tool. The target architecture is generally composed of a datapath and a controller; when fixed, it also fixes the performances of the synthesized design. The understanding of the target architecture is particularly important in order to evaluate and debug the result of behavioral synthesis.

A data path allocation system called SAM (simultaneous allocation by merging) is described. It exploits the tradeoff between the mapping from variables to registers and from operations to function units to reduce the amount of interconnection. It also exploits the tradeoff among the number of function units, the number of registers, and the amount of interconnection to minimize the total cost of data path. The latter feature is unique to the SAM system. This flexibility allows the SAM system to produce good data paths. Experimental results of the SAM system are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The importance of effective lower bound estimation (LBE) techniques is well established in high-level synthesis (HLS) since it allows more efficient exploration of the design space while providing other HLS tools with the capability of predicting the effect of specific tools on the design space. Much of the previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. With the push toward submicron technologies, simple models that use functional unit resources alone are not accurate enough to allow effective design space exploration since the effects of storage and interconnect can indeed dominate the cost function. In this paper, we present an integrated approach aimed at predicting lower bounds on hardware resources needed to implement a behavioral description within a given amount of time. Our area cost model accounts for storage (register) and interconnect resources (buses) in addition to functional resources. Our timing model uses a finer granularity that permits the modeling of functional unit, register, and interconnect delays. Our approach is integrated because we consider the dependencies between the different types of resources as well as the ordering in which the resources are allocated. We tested our technique for functional unit, storage, and interconnect requirements on several high-level synthesis benchmarks, and observed near-optimal results. We believe that our comprehensive LBE approach can lead to better quality HLS solutions in less time, and we demonstrate this approach in our paper.

Power gating is the most effective technique to reduce the leakage power of an idle functional unit. However, when the functional unit is turned on, a sudden discharge, called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In this paper, we point out the high-level synthesis (including operation scheduling and functional unit binding) has a great impact on the maximum surge current. Then, based on that observation, we propose an integer linear program (ILP) to formally draw up the surge current minimization problem in the high-level synthesis stage. Compared with the existing design flow, benchmark data show that our approach can significantly reduce the maximum surge current without any design overhead.

This paper deals with integrating an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The resulting environment provides a cycle based simulation of a behavioral module under synthesis. The simulator and the behavioral synthesis are based on a single model that allows one to link the behavioral description and the architecture produced by synthesis. The basic simulation-synthesis model is extended in order to allow for concurrent architectural simulation of several modules under synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

A new method that integrated high level synthesis and floorplan are proposed to reduce the total power dissipation. Function units are sorted into several clusters according to their working voltages. Floorplan are executed with the information of cluster gained from high level synthesis, and then the high level synthesis resolutions are adjusted iteratively with the interconnect information and switching activity gained from floorplan. Not only function unit power and interconnect power, but also the voltage converting power can be reduced in our method. Experimental results indicate that, under the given resource and latency constrains, the interconnect power, level convert power and total power of our method can be reduced by 30.4%, 35.1% and 22.9% respectively.