Cross-scale efficient tensor contractions for coupled cluster computations through multiple programming model backends

A scalable approach computes in operationally-compatible time the energy dispatch under uncertainty for electrical power grid systems of realistic size with thousands of scenarios. The authors propose several algorithmic and implementation advances in their parallel solver PIPS-IPM for stochastic optimization problems. New developments include a novel, incomplete, augmented, multicore, sparse factorization implemented within the PARDISO linear solver and new multicore- and GPU-based dense matrix implementations. They show improvement on the interprocess communication on Cray XK7 and XC30 systems. PIPS-IPM is used to solve 24-hour horizon power grid problems with up to 1.95 billion decision variables and 1.94 billion constraints on Cray XK7 and Cray XC30, with observed parallel efficiencies and solution times within an operationally defined time interval. To the authors' knowledge, "real-time"-compatible performance on a broad range of architectures for this class of problems hasn't been possible prior to this work.

Large-scale datasets in computational chemistry typically require distributed-memory parallel methods to perform a special operation known as tensor contraction. Tensors are multidimensional arrays, and a tensor contraction is akin to matrix multiplication with special types of permutations. Creating an efficient algorithm and optimized im- plementation in this domain is complex, tedious, and error-prone. To address this, we develop a notation to express data distributions so that we can apply use automated methods to find optimized implementations for tensor contractions. We consider the spin-adapted coupled cluster singles and doubles method from computational chemistry and use our methodology to produce an efficient implementation. Experiments per- formed on the IBM Blue Gene/Q and Cray XC30 demonstrate impact both improved performance and reduced memory consumption.

Research on programming distributed memory multiprocessors has resulted in a well‐understood programming model, namely data‐parallel programming. However, data‐parallel programming in a multithreaded environment is far less understood. For example, if multiple threads within the same process belong to different data‐parallel computations, then the architecture, compiler, or run‐time system must ensure that relative indexing and collective operations are handled properly and efficiently. We introduce a run‐time‐based solution for data‐parallel programming in a distributed memory environment that handles the problems of relative indexing and collective communications among thread groups. As a result, the data‐parallel programming model can now be executed in a multithreaded environment, such as a system using threads to support both task and data parallelism.

Transactional memory (TM) has been the focus of numerous studies, and it is supported in processors such as the IBM Blue Gene/Q and Intel Haswell. Many studies have used the STAMP benchmark suite to evaluate their designs. However, the speedups obtained for the STAMP benchmarks on all TM systems we know of are quite limited; for example, with 64 threads on the IBM Blue Gene/Q, we observe a median speedup of 1.4X using the Blue Gene/Q hardware transactional memory (HTM), and a median speedup of 4.1X using a software transactional memory (STM). What limits the performance of these benchmarks on TMs? In this paper, we argue that the problem lies with the programming model and data structures used to write them. To make this point, we articulate two principles that we believe must be embodied in any scalable program and argue that STAMP programs violate both of them. By modifying the STAMP programs to satisfy both principles, we produce a new set of programs that we call the Stampede suite. Its median speedup on the Blue Gene/Q is 8.0X when using an STM. The two principles also permit us to simplify the TM design. Using this new STM with the Stampede benchmarks, we obtain a median speedup of 17.7X with 64 threads on the Blue Gene/Q and 13.2X with 32 threads on an Intel Westmere system. These results suggest that HTM and STM designs will benefit if more attention is paid to the division of labor between application programs, systems software, and hardware.

Complex tensor contraction expressions arise in accurate electronic structure models in quantum chemistry, such as the Coupled Cluster method. Transformations using algebraic properties of commutativity and associativity can be used to significantly decrease the number of arithmetic operations required for evaluation of these expressions, but the optimization problem is NP-hard. Operation minimization is an important optimization step for the Tensor Contraction Engine, a tool being developed for the automatic transformation of high-level tensor contraction expressions into efficient programs. In this paper, we develop an effective heuristic approach to the operation minimization problem, and demonstrate its effectiveness on tensor contraction expressions for coupled cluster equations.

Wireless Mesh Networks (WMNs) consist of a high-density of hundreds to thousands of mesh routers (MRs) deployed in corporate offices and university campuses. The main purpose of this deployment is to meet user demands for high bandwidth, mobility, and reliability. However, our recent consideration of such networks revealed that they are rarely used at their peak capacity besides the fact that the entire MRS remains active continuously. Thus, during lower traffic periods the energy consumption is the same as in busy hours, while it would be possible to save a large amount of power. Green networking has recently been proposed; consist of rethink how networks are constructed and operated so that not only the cost and performance are taken into consideration but also their energy consumption and carbon footprint. In this paper, we draw attention that a large part of idle MRs results in considerable energy losses. Thousands of WMNs worldwide jointly aggravate this problem, while raising serious worry about the energy wastage that will happen in the future. In response to this problem, we first propose an optimal approach called Optimal Energy Efficiency Management Design (OEEMD) by formulating the problem as a Mixed Integer Linear Program (MILP) model to investigate the power consumption in WMN. As this problem is known to be NP-hard, we then propose an efficient heuristic algorithm called Green Energy Efficiency Management Design (GEEMD) for wireless mesh networks. GEEMD uses a sleep mechanism to power on/off underutilized MRs, based on the traffic load and solar energy generation. For the performance evaluation, we used OEEMD and GEEMD to study the performance of WMN deployment scenario in the university and campus area of Tlemcen city in Algeria over dynamic traffic profiles. Illustrative numerical examples show that, with suitable design parameters, we can efficiently reduce energy consumption in WMN without significantly impacting the network performance.

Enabling simulation at the fifth rung of DFT: Large scale RPA calculations with excellent time to solution

Simultaneous re-design and scheduling of multiple effect evaporator systems

A highly flexible, distributed multiprocessor architecture for network processing

Loop tiling is a key high-level transformation which is known to maximize locality in loop intensive programs. It has been successfully applied to a number of applications including tensor contractions, iterative stencils and machine learning. This technique has also been extended to a wide variety of computational domains and architectures. The performance achieved with this critical transformation largely depends on a set of inputs given, the tile sizes, due to the complex trade-off between locality and parallelism. This problem is exacerbated in GPGPU architectures due to limited hardware resources such as the available shared-memory. In this paper we present a new technique to compute resource conscious tile sizes for affine programs. We use Integer Linear Programming (ILP) constraints and objectives in a cross-compiler fashion to faithfully and effectively mimic the transformations applied in a polyhedral GPU compiler (PPCG). Our approach significantly reduces the need for experimental auto-tuning by generating only two tile size configurations that achieve strong out-of-the-box performance. We evaluate the effectiveness of our technique using the Polybench benchmark suite on two GPGPUs, an AMD Radeon VII and an NVIDIA Tesla V100, using OpenCL and CUDA programming models. Experimental validation reveals that our approach achieves nearly 75% of the best empirically found tile configuration across both architectures.

LPARX provides efficient run-time support for dynamic, non-uniform scientific calculations running on MIMD distributed memory architectures. It extends HPF's data decomposition model to provide support for dynamic, block irregular data structures. LPARX represents data decompositions as first-class objects and expresses data dependencies in a manner which is logically independent of data decomposition and problem dimension. LPARX applications are portable across a diversity of MIMD machines. We have implemented a number of applications in LPARX-including a 3D particle calculation and 2D and 3D adaptive multigrid solvers-which could not have been efficiently implemented in HPF. >

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