Cryo-CMOS Analog Circuits for Spin Qubit Control

Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'.<br/><br/>In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. <br/><br/>Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended.<br/><br/>In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. <br/><br/>We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. <br/><br/>One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.

This paper presents a Digital-to-Analog Converter (DAC) for shuttling operations in a trapped-ion quantum computer (TIQC) measured at 4.6 K.We provide an extensive analysis and comparison of measured characteristics at room temperature (RT) versus those at cryogenic temperature (CT), particularly focusing on the DAC’s static and dynamic behavior, as well as its noise performance. By making well-conceived analytical design choices, we show that the DAC’s performance at CT can match its performance at RT. This is achieved through sufficient design margins, the selection of suitable components, and the adjustment of biasing voltages. The investigated chip features a 12 bit, resistive R-2R ladder-based DAC, which also comprises an input buffer for the DAC’s reference voltage and a simplistic SPI to read the digital control words. Implemented in Infineon’s 130nm Bipolar-CMOS-DMOS (BCD) technology, the DAC consumes 1.1mW from a 1.5V power supply at RT. Its power consumption increases to around 1.5mW at CT due to necessary biasing adjustments. The DAC’s linearity, characterized by its Differential-Non-Linearity (DNL) and Integral-Non-Linearity (INL) remains almost unchanged across temperatures, aligning with its Spurious-Free Dynamic Range (SFDR). The slew-rate (SR) decreases toward CT compared to RT. While the thermal noise floor also decreases, the low-frequency noise increases at CT. Overall, this leads to a slight decrease in the DAC’s noise performance at 4.6K.

Donor electron spin qubits hosted within nanoscale devices have demonstrated seconds-long relaxation times at magnetic fields suitable for the operation of spin qubits in silicon of $B=1.5\phantom{\rule{0.16em}{0ex}}\mathrm{T}$. The relaxation rates of these qubits have been shown at milliKelvin temperatures to be mediated by spin-orbit coupling with a ${B}^{5}$ dependency on magnetic field for $B>3\phantom{\rule{0.16em}{0ex}}\mathrm{T}$ with a transition to a ${B}^{3}$ dependency at magnetic fields below ($B\ensuremath{\le}3\phantom{\rule{0.16em}{0ex}}\mathrm{T}$). This deviation has been observed in many spin qubit systems but is particularly notable in multidonor quantum dot qubits. The reason for this has remained a mystery. In this paper we show that for these multidonor low noise, crystalline qubits this deviation at low magnetic fields can be explained by a hyperfine mediated relaxation mechanism of the electron spin through a quantitative model of the relaxation rates. This model identifies the importance of donor nuclear spin flips which are more apparent in multidonor systems in which the larger numbers of donor nuclei creates stronger confinement potentials and enhanced hyperfine couplings. We show theoretically that with atomic precision engineering of the locations of the donor nuclei in these multidonor quantum dot qubits, and/or nuclear spin control, we can minimize the hyperfine mediated relaxation allowing ${T}_{1}$ to extend to $\ensuremath{\sim}200$ seconds ($B=1.5\phantom{\rule{0.16em}{0ex}}\mathrm{T}$).

Real-time sensing of (spin-dependent) single-electron tunneling is fundamental to electrical readout of qubit states in spin quantum computing. Here, we demonstrate the feasibility of detecting such single-electron tunneling events using an atomically planar charge sensing layout, which can be readily integrated in scalable quantum computing architectures with phosphorus-donor-based spin qubits in silicon (Si:P). Using scanning tunneling microscopy (STM) lithography on a Si(001) surface, we patterned a single-electron transistor (SET), both tunnel and electrostatically coupled to a coplanar ultrasmall quantum dot, the latter consisting of approximately four P donors. Charge transitions of the quantum dot could be detected both in time-averaged and single-shot current response of the SET. Single electron tunneling between the quantum dot and the SET island on a time-scale (τ ∼ ms) two-orders-of-magnitude faster than the spin-lattice relaxation time of a P donor in Si makes this device geometry suitable for projective readout of Si:P spin qubits. Crucial to scalability is the ability to reproducibly achieve sufficient electron tunnel rates and charge sensitivity of the SET. The inherent atomic-scale control of STM lithography bodes extremely well to precisely optimize both of these parameters.

We investigate the effect of the valley degree of freedom on Pauli-spin blockade readout of spin qubits in silicon. The valley splitting energy sets the singlet-triplet splitting and thereby constrains the detuning range. The valley phase difference controls the relative strength of the intra- and inter-valley tunnel couplings, which, in the proposed Pauli-spin blockade readout scheme, couple singlets and polarized triplets, respectively. We find that high-fidelity readout is possible for a wide range of phase differences, while taking into account experimentally observed valley splittings and tunnel couplings. We also show that the control of the valley splitting together with the optimization of the readout detuning can compensate the effect of the valley phase difference. To increase the measurement fidelity and extend the relaxation time we propose a latching protocol that requires a triple quantum dot and exploits weak long-range tunnel coupling. These opportunities are promising for scaling spin qubit systems and improving qubit readout fidelity

Quantum computation requires high-fidelity single-qubit and two-qubit gates on a scalable platform. Silicon spin qubits are a promising platform toward realization of this goal. In this paper we show how to perform single-qubit and controlled-Z (cz) gates in a linear chain of three spin qubits with always-on exchange coupling, which is relevant for certain dot- and donor-based silicon devices. We also show how to make the cz gate robust against both charge noise and pulse length error using a two-tone pulse shaping method. The robust pulse maintains a fidelity of 99.99% at 3.5% fluctuations in exchange or pulse amplitude, which is an improvement over the uncorrected pulses where this fidelity can only be maintained for fluctuations in exchange up to 2% or up to 0.2% in amplitude.

We demonstrate that exciting possible realizations of quantum Floquet matter are within reach for modern silicon spin qubits based in quantum dots, most notably the discrete time crystal (DTC). This is significant given that spin qubits have fallen behind other qubit architectures in terms of size and control. However, silicon spin qubits are especially well suited to this task as the charge noise that usually foils gate operations can now be leveraged as an asset in this time-crystal realization. We illustrate differences between prethermal phenomena and true time-crystalline spatiotemporal order. We demonstrate that even for a spin chain of four qubits, rich regime structures can be established by observing signatures of the discrete time crystal and the Floquet symmetry-protected topological regime both distinct from the thermal regime. We also analyze the persistence of these signatures at longer chain lengths, showing that the DTC lifetime grows exponentially with the system length and that these signatures may even be detectable for chains as small as three qubits. We also discuss the effects of longer pulse durations and the effectiveness of pulse sequences for converting the exchange interaction to an Ising model. Our theoretical predictions are well suited for immediate experimental implementations using currently existing quantum dot spin qubit systems.

We address the experimentally relevant problem of robust mitigation of dephasing noise acting on a qubit. We first present an extension of the method of Kuopanportti et al. [Phys. Rev. A 77, 032334 (2008)] for representing $1/{\ensuremath{\omega}}^{\ensuremath{\alpha}}$ noise to the efficient representation of arbitrary Markovian noise. We then add qubit control pulses to enable the design of numerically optimized, two-dimensional, bounded amplitude control functions capable of decoupling the qubit from the dephasing effects of a broad variety of Markovian noise spectral densities during one- and two-qubit quantum operations. We illustrate the method with development of numerically optimized control pulse sequences that minimize decoherence due to a combination of $1/\ensuremath{\omega}$ and constant-offset noise sources. Comparison with the performance of standard dynamical decoupling protocols shows that the numerically optimized pulse sequences are considerably more robust with respect to zero-frequency noise. Application to the mitigation of dephasing noise on spin qubits in silicon indicates that high-fidelity quantum gates may, in principle, be implemented for such qubits with the assistance of current pulse-generation technology.

High-speed high resolution analog-to-digital converter (ADC) is the key design blocks in mixed-signal chip design since the ADC is an interface between digital signal processing systems and the analog world. With the rapid advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power ADCs that can be realized in a mainstream deep sub-micrometer CMOS technology. On the other hand, since analog circuits tend to be sensitive to fluctuations in temperature and the fabrication process, circuit designers are forced to allow for a wide margin to ensure the desired operation of all the chips under various conditions. Therefore, if the margins can be minimized, both reduction of power dissipation and a higher yield in mass production can be achieved. To tap onto the waves of the rapid booming wireless communication markets, high resolution and high speed A/D converter is required at very low power consumption. Providing the wanted resolution at the required speed for the minimum power consumption and silicon cost is what's driving the use of specific A/D architectures [1]. Architectures that have been applied include flash, subranging, successive approximation, sigma-delta and pipelined. Each of these architectures has their specific advantages and drawbacks. Pipelined architecture poised as a suitable candidate since the power consumption will be an order of magnitude better comparing to flash ADC, subranging ADC, successive approximation ADC and oversampling ADC. Moreover, a correction algorithm can be employed to compensate for the errors in the sub-ADC. Shooting for even higher speed, parallelism is required to be incorporated into pipelined structure. Hence, in this work, a feasibility study of a novel subranging pipelined A/D converter with 100 MS/s and 8-bit resolution is conducted. This research describes the design of a 8-bit 100 MS/s subranging pipelined analog-to-digital converter(ADC) suitable for wide-range applications. To achieve the wide-range performance, this work purposes a novel architectural design at both system and circuit levels. At the device level, device modeling and active components characterisations are carefully studied. Thin gate oxide, NFET is fabricated in Chartered 90nm CMOS process. The results showed that the models used in SPIC simulation correlate well with the measured results except at the end of high VDD where breakdown is seen in the measured results but not during simulation. At the circuit level, a 3-bit coarse ADC and a 6-bit fine ADC are developed. Logic designs are also carried out. At the system level, this work investigates the effects of ADC design parameters such as DNL and INL in the static DC aspects and SFDR and ENOB in the dynamic AC aspects. A top-down design methodology is adopted in this work. The behavioral modelling results verify the success of the proposed architecture. The simulation results showed that the designed ADC is able to achieve a 7.4 effective bits out of 8 bit resolution.

The recent decade has witnessed substantial advancements in silicon quantum computing. Important milestones include demonstrations of quantum gates exceeding the fault-tolerance threshold, high-fidelity single-shot spin readout, hot quantum bits (hot qubits), and compact scalable spin arrays. Silicon qubits hold promise to leverage semiconductor industry technologies into scalable qubit manufacturing. Both the academic and industry communities are striving to push this advantage into reality. However, formidable challenges persist in the quest to develop a fully operational universal quantum computer. This review focuses on single-spin qubits in silicon. First, we start with foundational spin qubit theory. Then, we discuss gate-defined quantum dots and donor dot systems, with a particular emphasis on two-qubit gate operations and the scalability of qubit arrays. Lastly, we address long-distance coupling, highlighting key areas for future research and potential scale-up strategies for this rapidly evolving field.

Fault-tolerant quantum computers that can solve hard problems rely on quantum error correction1. One of the most promising error correction codes is the surface code2, which requires universal gate fidelities exceeding an error correction threshold of 99 per cent3. Among the many qubit platforms, only superconducting circuits4, trapped ions5 and nitrogen-vacancy centres in diamond6 have delivered this requirement. Electron spin qubits in silicon7-15 are particularly promising for a large-scale quantum computer owing to their nanofabrication capability, but the two-qubit gate fidelity has been limited to 98 per cent owing to the slow operation16. Here we demonstrate a two-qubit gate fidelity of 99.5 per cent, along with single-qubit gate fidelities of 99.8 per cent, in silicon spin qubits by fast electrical control using a micromagnet-induced gradient field and a tunable two-qubit coupling. We identify the qubit rotation speed and coupling strength where we robustly achieve high-fidelity gates. We realize Deutsch-Jozsa and Grover search algorithms with high success rates using our universal gate set. Our results demonstrate universal gate fidelity beyond the fault-tolerance threshold and may enable scalable silicon quantum computers.

Shuttling spins with high fidelity is a key requirement to scale up semiconducting quantum computers, enabling qubit entanglement over large distances and favoring the integration of control electronics on-chip. To decouple the spin from the unavoidable charge noise, state-of-the-art spin shuttlers try to minimize the inhomogeneity of the Zeeman field. However, this decoupling is challenging in otherwise promising quantum computing platforms such as hole spin qubits in silicon and germanium, characterized by a large spin-orbit interaction and an electrically tunable qubit frequency. In this work, we show that, surprisingly, the large inhomogeneity of the Zeeman field stabilizes the coherence of a moving spin state, thus also enabling high-fidelity shuttling in these systems. We relate this enhancement in fidelity to the deterministic dynamics of the spin that filters out the dominant low-frequency contributions of the charge noise. By simulating several different scenarios and noise sources, we show that this is a robust phenomenon generally occurring at large field inhomogeneity. By appropriately adjusting the motion of the quantum dot, we also design realistic protocols enabling faster and more coherent spin shuttling. Our findings are generally applicable to a wide range of setups and could pave the way toward large-scale quantum processors. Published by the American Physical Society 2024

Spin qubits in silicon are strong contenders for the realization of a practical quantum computer, having demonstrated single- and two-qubit gates with fidelities above the fault-tolerant threshold, and entanglement of three qubits. However, maintaining high-fidelity operations while increasing the qubit count remains challenging and therefore only two-qubit algorithms have been executed. Here we utilize a four-qubit silicon processor with all control fidelities above the fault-tolerant threshold and demonstrate a three-qubit Grover’s search algorithm with a ~95% probability of finding the marked state. Our processor is made of three phosphorus atoms precision-patterned into isotopically pure silicon, which localise one electron. The long coherence times of the qubits enable single-qubit fidelities above 99.9% for all qubits. Moreover, the efficient single-pulse multi-qubit operations enabled by the electron–nuclear hyperfine interaction facilitate controlled-Z gates between all pairs of nuclear spins with fidelities above 99% when using the electron as an ancilla. These control fidelities, combined with high-fidelity non-demolition readout of all nuclear spins, allow the creation of a three-qubit Greenberger–Horne–Zeilinger state with 96.2% fidelity. Looking ahead, coupling neighbouring nuclear spin registers, as the one shown here, via electron–electron exchange may enable larger, fault-tolerant quantum processors.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

PurposeThe purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.Design/methodology/approachA low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.FindingsCompared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.Originality/valueComparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.