Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding

Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE-754R). This work presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. The design uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a simplified combined decimal incrementer/decrementer. Synthesis results show that a 64-bit (16-digit) implementation of the decimal divider, which is compliant with IEEE-754R, has an estimated critical path delay of 0.69 ns when implemented using LSI Logic's 0.11 micron gflx-p standard cell library.

The IBM POWER6™ microprocessor core includes two accelerators for increasing performance of specific workloads. The vector multimedia extension (VMX) provides a vector acceleration of graphic and scientific workloads. It provides single instructions that work on multiple data elements. The instructions separate a 128-bit vector into different components that are operated on concurrently. The decimal floating-point unit (DFU) provides acceleration of commercial workloads, more specifically, financial transactions. It provides a new number system that performs implicit rounding to decimal radix points, a feature essential to monetary transactions. The IBM POWER™ processor instruction set is substantially expanded with the addition of these two accelerators. The VMX architecture contains 176 instructions, while the DFU architecture adds 54 instructions to the base architecture. The IEEE 754R Binary Floating-Point Arithmetic Standard defines decimal floating-point formats, and the POWER6 processor--on which a substantial amount of area has been devoted to increasing performance of both scientific and commercial workloads--is the first commercial hardware implementation of this format.

High performance microprocessors are protected against transient and early end of life failures using a variety of error detection and fault isolation technologies. Execution units can be protected with duplication, parity prediction, or residue checking. Residue checking has an advantage due to its small size. A modulus is selected based on the radix of the numbers being checked. In a decimal floating-point unit there are two types of numbers in different bases. There are base 10 decimal numbers and base 2 integers being used. A residue checking system that makes it easy to check both base 2 and 10 numbers is discussed. Current state of the art designs that are currently in use are described as well as a novel hybrid moduli 9 and 3 residue system. The checking systems for the decimal and binary floating-point units of some recent IBM microprocessors including the Power6, Power7, z10, and z196 microprocessors are detailed.

There is a significant demand for decimal arithmetic, especially in commercial and financial applications. Furthermore, specifications for decimal floating-point (DFP) formats and arithmetic operations have been added to the IEEE-754-2008 Standard. Hardware and software support for DFP arithmetic operations have been investigated, especially in the last decade. This paper presents a novel DFP fused multiply-add (DFP-FMA) unit and a new decimal leading-zero anticipator (LZA). The DFP-FMA design uses a previously published parallel fixed-point decimal multiplier for multiplication and a Kogge-Stone parallel prefix adder for decimal addition. The DFP-FMA unit is synthesized using LSI Logic's gflxp 65-nm CMOS standard cell library. Synthesis results show that a 1.07-ns cycle time is obtained when the unit is synthesized with five pipeline stages. Furthermore, a new decimal LZA presented in this paper predicts zero-digit positions exactly and reduces the latency of the DFP-FMA operation. The correctness of the new decimal LZA is fully tested.

High-speed datapaths in microprocessors and embedded processors contain complex floating-point (FP) arithmetic units which have a critical role in the processor's performance. Although the FP units' complex structure consists of classic integer arithmetic components, the embedded components encounter serious testability problems due to their limited accessibility from the FP unit ports and testability loss due to FP unit inherent operations, such as rounding and normalization. In this paper, we analyze the testability problems and present scalable test generation for FP units using as a demonstration vehicle the popular, high-speed, two-path architecture of the most complex unit, the FP adder. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. The identified test conditions can be utilized with respect to any fault model and are independent of the internal structure and the size of the components. Thus, they can be applied to FP adders of various exponent and significant sizes (single, double, and custom precision), as well as to other types of FP units, which also consist of classic integer arithmetic components similarly interconnected

In this work, we propose a new decimal redundant CORDIC algorithm to manage transcendental functions, using floating-point representation. The algorithms determine the direction of the elementary rotation using sign estimations. Unlike binary redundant CORDIC, repetition of iterations are not required to ensure convergence since novel decimal codes have been carefully selected with sufficient redundancy to prevent any repetition. The algorithms are mapped to a low-cost unit based on a decimal 3-2 carry-save adder which can also be used as a floating-point decimal division unit. Compared to current decimal floating-point units, the implementation of our algorithm involves minor modifications of the native hardware, while providing a huge set of elementary functions.

본 논문에서는 동일한 크기의 지수를 갖는 십진 부동소수점 오퍼랜드의 가산 및 감산연산을 빠르게 하기 위해, 두 개의 데이터 경로를 가지는 십진 부동소수점 가산기를 제안한다. 제안된 십진 부동소수점 가산기는 L. K. Wang의 오퍼랜드 정렬 계획을 사용하지만 오퍼랜드의 지수 크기가 같을 경우 정밀도를 보장하는 범위 내에서 속도 향상을 위해 고속의 데이터 경로를 통해 연산한다. 제안된 가산기의 성능 평가를 위해 Design Compiler에서 SMIC사의 0.18㎛ CMOS 공정 테크놀로지 라이브러리를 이용하여 합성하였다. 합성 결과 면적은 L. K. Wang의 가산기와 비교하여 8.26% 증가하였지만 전체 임계경로의 지연시간이 10.54% 감소하였다. 또한 같은 크기의 지수를 가지는 오퍼랜드를 연산할 때는 임계경로보다 13.65% 단축된 경로에서 연산을 수행하는 것을 확인하였다. 제안한 십진 부동소수점 가산기 구조는 동일 크기의 지수를 가지는 오퍼랜드의 비중이 2%이상일 때 L. K. Wang의 가산기 구조 대비 효용성이 높다.

Processor design is a widely studied topic in computer system architecture design. How to improve computer performance is an important part of the computer overall design. In general processors, multiplication components play a decisive role in processor's performance. An important and frequent operation in decimal computations is multiplication. However, due to the inherent inefficiency of decimal arithmetic implementations in binary logic, practically all the proposed decimal multipliers are sequential units. Binary computing couldn't be avoided of conversion efficiency lowly and loss of accuracy. In this paper direct expanding the decimal computing applications and binary can't meet the needs of decimal operations, according to this new standard IEEE-754r, use SOPC technology design and implement a new architecture based on the decimal floating-point multiplication unit. This design takes advantage of flexibility and low-power of SOPC, the independence of IP core and so on; it is packaged as an independent IP core. This decimal floating-point multiplication unit is broadly applications in the general processors, portable devices, and mass data processing and so on. It uses Signed-Digit radix-4 algorithm and new BCD coding techniques for the decomposition of decimal floating-point computing. and compared with the common single-precision binary floating-point unit, it was wider computing, higher accuracy, faster computing speed and wider application. The main contributions of this paper include: (1) Customized a 32/64 bit fully functional decimal floating point multiplication IP core; (2) Improved partial products based on the BCD-8421 and revised parts of the circuit; (3) According to the customized component operational requirements, defined a way of data bus, caused decimal floating point multiplication unit is good access SOPC system bus. This unit can be well used to processors, which support the standard of decimal floating-point operations, to improve processor performance. This model is verified by synthesis to Altera's low cost Cyclone ¢o FPGA.

Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating-point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating-point arithmetic. This offloads compute-intensive tasks from the primary processor and overcomes floating-point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating-point units are slower than the fixed-point counterparts. One of the popular ways to improve the speed of floating-point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multi-operand adders. Butterfly units are designed, in two of the most recent works, using three-operand and four-operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five-operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster.

Field Programmable Gate Arrays (FPGAs) are commonly used to accelerate floating-point (FP) applications. Although researchers have extensively studied FPGA FP implementations, existing work has largely focused on standalone operators and frequency-optimized designs. These works are not suitable for FPGA soft processors which are more sensitive to latency, impose a lower frequency ceiling, and require IEEE FP standard compliance. We present an open-source floating-point unit (FPU) for FPGA RISC-V soft processors that is fully IEEE compliant with configurable levels of FP precision. Our design emphasizes runtime performance with 25% lower latency in the most common instructions compared to previous works while maintaining efficient resource utilization. Our FPU also allows users to explore various mantissa widths without having to rewrite or recompile their algorithms. We use this to investigate the scalability of our reduced-precision FPU across numerous microbenchmark functions as well as more complex case studies. Our experiments show that applications like the discrete cosine transformation and the Black-Scholes model can realize a speedup of more than 1.35x in conjunction with a 43% and 35% reduction in lookup table and flip-flop resources while experiencing less than a 0.025% average loss in numerical accuracy with a 16-bit mantissa width.

Signal processing and image processing applications require floating-point computation in digital circuit designs. The floating-point calculation is recommended in almost all digital design applications to improve the accuracy of results. Different mathematical operations use floating-point mathematical operations and can be used to perform calculations and different logical units. The proposed work sugestes a double-MAF unit that uses radix-8 for multiplication and uses a common addition block for addition and multiplication operations. Firstly, floating-point numbers are transformed into IEEE 754 format, next to both addition and multiplication calculations are achieved. Extracts the fractional part of a number and performs a calculation based on the exponential difference between the numbers. The proposed curriculum is designed with a parallel structure that first extracts the decimal and exponential values of the first unit and then performs multiplication and addition operations in the second block. At last, the output is made in the third block where normalization and zero detection are performed. The proposed approach is then compared to the baseline approach, which shows improvements in energy consumption and maximum common path delay. The results showed that the delay is reduced by about 57%.

In digital circuits, particularly space signal applications, the detection/estimation of phase (angle) like milli degree is challenging and involves many complex operations.To estimate milli degree (10-3) or more, floating point operations (like double precision adders, subtractions, multiplications, and divisions) are the significant components and power and area consumption; delays are more in existing works.Existing works mainly concentrate on clock-based synchronous operations, which require more hold, and clock distribution is another major problem due to extra circuitry requirements.The proposed pipelined and clock-efficient distribution system (CEDS) is incorporated in the Floating-Point Unit (FPU) design to address these issues.It includes a double-precision adder, multiplication, division, and subtraction.These FPU and CEDS can be used to detect Milli Degree for GHz frequency in Space applications more accurately.The floating points are essential in phase shift operation used in the space-borne system for effective correction of error checking rather than execution of error analysis in the real-time scenario.Modern digital circuits can hardly improve due to limitations of physical area consumption.The substitution for these limitations, the new digital ternary logic (0, 1, 2), is the solution because of its higher number of digital circuits involved in floating points.The ternary logic is the best solution for the minimization of number bits to optimize memory utilization, and ternary logic has Negative Ternary Inverter (NTI), Ternary Decrement Cycling Inverter (DCI), Standard Ternary Inverter (STI,) and Positive Ternary Inverter (PTI).The proposed design is successfully designed and validated on Zybo Z7-10 (XC7Z010-1CLG400C) FPGA development board.The results show a 45% reduction in power consumption, delay, and area utilization.

We present a non-intrusive concurrent error detection (CED) method for protecting the control logic of a contemporary floating point unit (FPU). The proposed method is based on the observation that control logic errors lead to extensive datapath corruption and affect, with high probability, the exponent part of the IEEE 754 floating point representation. Thus, exponent monitoring can be utilized to detect errors in the control logic of the FPU. Predicting the exponent involves relatively simple operations, therefore our method incurs significantly lower overhead than the classical approach of duplicating the control logic of the FPU. Indeed, experimental results on the openSPARC T1 processor show that, as compared to control logic duplication, which incurs an area overhead of 17.9% of the FPU size, our method incurs an area overhead of only 5.8% yet still achieves detection of over 95% of transient errors in the FPU control logic. Moreover, the proposed method offers the ancillary benefit of also detecting 98.1% of datapath errors that affect the exponent, which cannot be detected via duplication of control logic. Finally, when combined with a classical residue code-based method for the fraction, our method leads to a complete CED solution for the entire FPU which provides a coverage of 94.4% of all errors at an area cost of 16.32% of the FPU size.

FPgen is a new test generation framework targeted toward the verification of the floating point (FP) datapath, through the generation of test cases. This framework provides the capacity to define virtually any architectural FP coverage model, consisting of verification tasks. The tool supplies strong constraint solving capabilities, allowing the generation of random tests that target these tasks. We present an overview of FPgen's functionality, describe the results of its use for the verification of several FP units, and compare its efficiency with existing test generators.

The floating-point unit (FPU) of the IBM z990 eServer™ is the first one in an IBM mainframe with a fused multiply-add dataflow. It also represents the first time that an SRT divide algorithm (named after Sweeney, Robertson, and Tocher, who independently proposed the algorithm) was used in an IBM mainframe. The FPU supports dual architectures: the zSeries® hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture. Six floating-point formats—including short, long, and extended operands—are supported in hardware. The throughput of this FPU is one multiply-add operation per cycle. The instructions are executed in five pipeline steps, and there are multiple provisions to avoid stalls in case of data dependencies. It is able to handle denormalized input operands and denormalized results without a stall (except for architectural program exceptions). It has a new extended-precision divide and square-root dataflow. This dataflow uses a radix-4 SRT algorithm (radix-2 for square root) and is able to handle divides and square-root operations in multiple floating-point and fixed-point formats. For fixed-point divisions, a new mechanism improves the performance by using an algorithm with which the number of divide iterations depends on the effective number of quotient bits.