Decimal floating-point division using Newton-Raphson iteration

Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 standard for binary floating-point arithmetic to include specifications for decimal floating-point arithmetic and IBM recently announced incorporating a decimal floatingpoint unit into their POWER6 processor. As processor support for decimal floating-point arithmetic emerges, it is important to investigate efficient algorithms and hardware designs for common decimal floating-point arithmetic algorithms. This paper presents novel designs for a decimal floating-point adder and a decimal floating-point multifunction unit. To reduce their delay, both the adder and the multifunction unit use decimal injection-based rounding, a new form of decimal operand alignment, and a fast flag-based method for rounding and overflow detection. Synthesis results indicate that the proposed adder is roughly 21% faster and 1.6% smaller than a previous decimal floating-point adder design, when implemented in the same technology. Compared to the decimal floating-point adder, the decimal floating-point multifunction unit provides six additional operations, yet only has 2.8%more delay and 9.7% more area.

There is a significant demand for decimal arithmetic, especially in commercial and financial applications. Furthermore, specifications for decimal floating-point (DFP) formats and arithmetic operations have been added to the IEEE-754-2008 Standard. Hardware and software support for DFP arithmetic operations have been investigated, especially in the last decade. This paper presents a novel DFP fused multiply-add (DFP-FMA) unit and a new decimal leading-zero anticipator (LZA). The DFP-FMA design uses a previously published parallel fixed-point decimal multiplier for multiplication and a Kogge-Stone parallel prefix adder for decimal addition. The DFP-FMA unit is synthesized using LSI Logic's gflxp 65-nm CMOS standard cell library. Synthesis results show that a 1.07-ns cycle time is obtained when the unit is synthesized with five pipeline stages. Furthermore, a new decimal LZA presented in this paper predicts zero-digit positions exactly and reduces the latency of the DFP-FMA operation. The correctness of the new decimal LZA is fully tested.

IEEE 754 floating-point arithmetic is widely used in modern, general-purpose computers. It is based on real arithmetic and is made total by adding both a positive and a negative infinity, a negative zero, and many Not-a-Number (NaN) states. Transreal arithmetic is total. It also has a positive and a negative infinity but no negative zero, and it has a single, unordered number, nullity. Modifying the IEEE arithmetic so that it uses transreal arithmetic has a number of advantages. It removes one redundant binade from IEEE floating-point objects, doubling the numerical precision of the arithmetic. It removes eight redundant, relational, floating-point operations and removes the redundant total order operation. It replaces the non-reflexive, floating-point, equality operator with a reflexive equality operator and it indicates that some of the exceptions may be removed as redundant - subject to issues of backward compatibility and transient future compatibility as programmers migrate to the transreal paradigm.

Even though decimal arithmetic is pervasive in financial and commercial transactions, computers are still implementing almost all arithmetic calculations using binary arithmetic. As chip real estate becomes cheaper it is becoming likely that more computer manufacturers will provide processors with decimal arithmetic engines. Programming languages and databases are expanding the decimal data types available while there has been little change in the base hardware. As a result, each language and application is defining a different arithmetic and few have considered the efficiency of hardware implementations when setting requirements. We propose a decimal format which meets the requirements of existing standards for decimal arithmetic and is efficient for hardware implementation. We propose this specification in the hope that designers will consider providing decimal arithmetic in future microprocessors and that future decimal software specifications will consider hardware efficiencies.

This chapter contains sections titled: Introduction Round-Off Error Propagation Induced by FP Computation The CESTAC Method, a Stochastic Approach for Analyzing Round-Off Error Propagation Stochastic Arithmetic Validation and Implementation of the CESTAC Method Discrete Stochastic Arithmetic (DSA) Taking into Account Data Errors The CADNA Library [36] The Use of the CADNA Library Can the CADNA Library Fail? Conclusion References

Most high-capacity, 3D data-hiding schemes introduce irreversible changes into the host model. For artistic or technical models, not modifying the original mesh models is sometimes very important. This work describes a novel, multi-layer, reversible data-hiding scheme for 3D mesh models. The proposed scheme starts with finding an independent set of vertices for embedding data. The prediction residues of the vertices and the secret bit string are then encoded using the arithmetic coding method. The embedding procedure is done by substituting part of the mantissa of these vertices with the coded arithmetic decimal numbers. A maximum distortion constraint is set for each embedding vertex, such that the distortion on the cover model is controlled to be imperceptible. Users can construct a multi-layer embedding scheme by repeatedly applying the single-layer embedding procedure until the secret bit string is completely embedded. By integrating the arithmetic encoder and the substitution operation, the proposed method achieves 4-8 bits/vertex embedding capacity while reserving the ability of rebuilding the original model. Experimental results show that the proposed scheme can successfully reconstruct the original model while extracting the secret bit string.

본 논문에서는 동일한 크기의 지수를 갖는 십진 부동소수점 오퍼랜드의 가산 및 감산연산을 빠르게 하기 위해, 두 개의 데이터 경로를 가지는 십진 부동소수점 가산기를 제안한다. 제안된 십진 부동소수점 가산기는 L. K. Wang의 오퍼랜드 정렬 계획을 사용하지만 오퍼랜드의 지수 크기가 같을 경우 정밀도를 보장하는 범위 내에서 속도 향상을 위해 고속의 데이터 경로를 통해 연산한다. 제안된 가산기의 성능 평가를 위해 Design Compiler에서 SMIC사의 0.18㎛ CMOS 공정 테크놀로지 라이브러리를 이용하여 합성하였다. 합성 결과 면적은 L. K. Wang의 가산기와 비교하여 8.26% 증가하였지만 전체 임계경로의 지연시간이 10.54% 감소하였다. 또한 같은 크기의 지수를 가지는 오퍼랜드를 연산할 때는 임계경로보다 13.65% 단축된 경로에서 연산을 수행하는 것을 확인하였다. 제안한 십진 부동소수점 가산기 구조는 동일 크기의 지수를 가지는 오퍼랜드의 비중이 2%이상일 때 L. K. Wang의 가산기 구조 대비 효용성이 높다.

This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device. The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

Scientific (and other) applications are critically dependent on calculations done using IEEE floating point arithmetic. A number of concerns have been raised about correctness in such applications given the numerous gotchas the IEEE standard presents for developers, as well as the complexity of its implementation at the hardware and compiler levels. The standard and its implementations do provide mechanisms for analyzing floating point arithmetic as it executes, making it possible to find and track problematic operations. However, this capability is seldom used in practice. In response, we have developed FPSpy, a tool that provides this capability when operating underneath existing, unmodified x64 application binaries on Linux, including those using thread- and process-level parallelism. FPSpy can observe application behavior without any cooperation from the application or developer, and can potentially be deployed as part of a job launch process. We present the design, implementation, and performance evaluation of FPSpy. FPSpy operates conservatively, getting out of the way if the application itself begins to use any of the OS or hardware features that FPSpy depends on. Its overhead can be throttled, allowing a tradeoff between which and how many unusual events are to be captured, and the slowdown incurred by the application, with the low point providing virtually zero slowdown. We evaluated FPSpy by using it to methodically study seven widely-used applications/frameworks from a range of domains (five of which are in the NSF XSEDE top-20), as well as the NAS and PARSEC benchmark suites. All told, these comprise about 7.5 million lines of source code in a wide range of languages, and parallelism models (including OpenMP and MPI). FPSpy was able to produce trace information for all of them. The traces show that problematic floating point events occur in both the applications and the benchmarks. Analysis of the rounding behavior captured in our traces also suggests the feasibility of an approach to adding adaptive precision underneath existing, unmodified binaries.

International audience

Decimal arithmetic has gained intensive attention in the last decade. Most commercial, financial, scientific, and internet-based applications need their data to be precise, while binary number system loses preciseness in some cases. The latency and area are two major factors in existing research works on decimal multiplication. However, energy/power consumption is another important factor in today’s digital systems. Hence, in this paper we proposed a new low power decimal adder based on prediction technique for decreasing the energy/power consumption of parallel decimal multiplication and show its impacts on one of the well-known parallel decimal multipliers architecture. Our observations show 11.5% improvement in terms of total power consumption and 10.13% improvement in terms of energy consumption.

The Automata Processor was designed for string-pattern matching. In this paper, we showcase its use to execute integer and floating-point comparisons and apply the same to accelerate interval stabbing queries. An interval stabbing query determines which of the intervals in a set overlap a query point. Such queries are often used in computational geometry, pattern matching, database management systems, and geographic information systems. The check for each interval is programmed as a single automaton and multiple automata are executed in parallel to provide significant performance gains. While handling 32-bit integers or single-precision floating-point numbers, up to 2.75 trillion comparisons can be executed per second, whereas 0.79 trillion comparisons per second can be completed for 64-bit integers or double-precision floating-point numbers. Additionally, our solution leaves the intervals in the set unordered; allowing addition or deletion of an interval in constant time. This is not possible for contemporary solutions wherein the intervals are ordered, making the query times faster, but making the updating of intervals complex. Our automata designs exemplify techniques that maximize resource utilization and minimize performance bottlenecks, which may be useful to future application developers on this processor. Their modular design allows them to become constituent parts of larger automata, where the numerical comparisons are part of the overall pattern matching operation. We have validated the designs on hardware, and the routines to generate the necessary automata and execute them on the AP will be made available as software libraries shortly.

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

The relative accuracy of (x+y)*(x-y)

Robust numerical calculation of tangent moduli at finite strains based on complex-step derivative approximation and its application to localization analysis