Defect Generation in Device Processing and Impact on the Electrical Performances

The electrical performance of single cell of anode-supported planar solid oxide fuel cell (SOFC) received much concern. In this paper, measurement principle, design method and experimental processes of the electrical performance test device for SOFC single cell were introduced. The fluid system of the device consisted of flowmeters, valves, tubes, furnace, etc. The measurement system of the device consisted of digital direct current voltage meter, chromatography work station, and industrial computer, etc. The operator could aquire the test data by the electronic load and work station operation software in the industrial computer.

Summary form only given. Since it was introduced in 2007 at Illinois, replica molding technique has been applied to fabricate microplasma devices on polymer substrates. Using the replica molding process, lightweight, transparent, and flexible microplasma device was fabricated for various potential applications such as flexible displays, light sources, and medical phototreatment tools. Although several flexible displays using microplasmas or other technologies have been reported, the reliability of device performance in several thin film technologies, requires further improvement because of mechanical fatigue and device contamination due to outgassing or permeation out of the flexible device components. This work describes the fabrication of microplasma devices and arrays by a replica molding process in which the substrate is a flexible and transparent plastic film. In particular, in this research, ultra-thin flexible glass substrates were embedded into the device so as to minimize outgassing of undesirable gas species and reinforce flexible substrates from the fatigue. Several large scale devices and arrays have been demonstrated to date and extended discharge lifetime of the device has been observed. Their electrical performance and optical characteristics as a function of long term operation will be discussed.

This paper describes the use of the Design of Experiments (DOE) technique with an accurate and efficient physical model. This approach allows for the systematic study of the effects of device geometry and process variations on electrical performance and demonstrates efficiently which parameters have the largest effect on device performane as well as showing any significant interaction between the effects. The model is used to show the variation in performance for a double recessed device.

In this work, the electrical and optical performance of AlGaN-based ultraviolet-C light-emitting diodes (UVC-LEDs) with a tapered Al-content hole injection layer was investigated both theoretically and experimentally. A total of 1000 h of real-time electrical stress was conducted to study the degradation process of such devices. UVC-LED incorporating a hole injection layer with a larger gradient was found to significantly suppress the degradation process compared to a sample with a smaller tapering gradient. Marginal efficiency droop of only 4.55% as well as 66% improved light output power, were identified for the proposed design under a current density of approximately 100 A/cm2. It was unambiguously demonstrated that UVC-LED with a greatly tapered hole injection layer facilitates both electron blocking and hole injection, providing a promising pathway towards the development of high-efficiency UV emitters.

The effect of a bi-layer structure by varying the Hf composition in Hf-silicate dielectric in improving the electrical performance and reliability of high-/spl kappa/ gate stack n-MOSFETs has been investigated. Introducing Hf-silicate with 19.5% of Hf composition at the bottom layer and 28.5% of Hf on the top of it reduces the leakage current dramatically, while it minimally sacrifices increase in equivalent oxide thickness. Moreover, the structure reduces defect generation rate under gate injection and improves breakdown voltage in comparison to the control samples. Increase in Si-O bonds at the bottom interface, decrease in Coulomb scattering, and increase in dielectric constant in the top layer have been attributed to the overall performance increase of the gate stack.

We report the effect of repeated tensile bending stress on the electrical performance of amorphous-indium–gallium–zinc-oxide (a-IGZO) thin-film transis- tors (TFTs) with source/drain offset. The tensile strain induces the negative transfer shift for the conventional TFTs, but the ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) increases significantly for the offset TFTs with negligible change in threshold voltage ( ${V}_{\textsf {TH}}$ ). The experimental results can be fitted well with technology computer aided design simulation by the generation of donor-like states in the bending region of the a-IGZO semiconductor. The degraded TFT performance can be completely recovered by thermal annealing at 250 °C for 1 h, confirming the generation of the donor-like metastable defects, oxygen vacancies.

Selected area heteroepitaxial growth of GaAs on silicon for advanced device structures

The purpose of this study is to report polishing characteristics of W CMP with combination sets of slurry and pad in 0.25 um logic technology. W etch back process is compared with W CMP process in view of electrical performance in the 0.25 /spl mu/m logic device. The proper selection of consumables is important to the successful application of W CMP. The W CMP process should be carefully controlled to be implemented in the back-end process of sub-quarter micron logic device.

Hybrid bonding technology has emerged as a critical 3D integration solution for advanced semiconductor packaging, enabling simultaneous bonding of metal interconnects and dielectric materials. However, conventional hybrid bonding processes face significant contamination challenges during O2 plasma treatment required for OH group formation on SiCN or the other dielectric material surfaces. The aggressive plasma conditions cause Cu sputtering and metal migration, leading to chamber and substrate contamination that accumulates over time and degrades process reliability. In this work, we present a novel approach to address these contamination issues by implementing a molybdenum disulfide (MoS2) barrier layer formed through plasma-enhanced chemical vapor deposition (PECVD) sulfurization of Mo films. The ultrathin MoS2 layer acts as an effective barrier preventing Cu sputtering during O2 plasma processing, thereby eliminating chamber contamination, and it also enables post-bonding electrical connectivity through controlled Cu filament formation via memristive switching mechanisms. When voltage is applied to the Cu-MoS2-Cu structure after hybrid bonding, Cu ions migrate through the MoS2 layer to form conductive filaments, establishing reliable electrical connections without compromising the bonding interface integrity. This innovative approach successfully resolves the fundamental contamination problem in hybrid bonding while maintaining excellent electrical performance, offering a pathway toward contamination-free and high-yield hybrid bonding processes for next-generation 3D-integrated devices.

Background and purpose To realize monolithic three-dimensional LSI and flexible mobile devices, it is essential to form semiconductor thin-film transistors (TFTs) on an insulator at low temperatures (<500 °C). Germanium (Ge) has garnered significant attention as a promising material for these applications due to its high carrier mobilities (electron: 3,900 cm²/V·s, hole: 1,900 cm²/V·s) and low crystallization temperature. We have successfully synthesized high-quality polycrystalline (poly-) Ge thin films using an advanced solid-phase crystallization (SPC) technique [1,2] and have fabricated accumulation-mode p-channel TFTs with excellent electrical properties [3]. More recently, we also demonstrated inversion-mode n-channel TFTs and CMOS inverter on SPC poly-Ge [4,5]. However, further improvements are needed, particularly in enhancing the ON/OFF ratio [4]. To address this, we aim to reduce OFF-state leakage current by shrinking the channel width, which is expected to significantly improve the ON/OFF ratio of n-channel poly-Ge TFTs. Experiments The TFT was fabricated on a poly-Ge/glass substrate, with details of the SPC process provided elsewhere [1]. The fabrication process flow and device structure are illustrated in Fig. 1. To form the n-type source/drain (S/D) regions, phosphorus (P) ion implantation was carried out at an energy of 50 keV and a dose of 1×10¹⁵ cm⁻². Following implantation, annealing was performed at 500 °C for 2 hours to activate and recrystallize the implanted regions. The active region was then defined by SPC-Ge isolation etching, followed by backfilling with sputter-deposited SiO₂. Two different island shapes—conventional rectangular and dumbbell-shaped channel TFT patterns—were formed on the same chip, as shown in the microscope images in Fig. 1. Next, the Ge surface was cleaned using plasma sacrificial oxidation followed by wet treatment. A stacked gate insulator consisting of GeO₂ (3 nm) and SiO₂ (20 nm) was then deposited. Post-deposition annealing (PDA) was performed at 400 °C for 30 minutes in N₂ to improve the gate dielectric quality. For the gate and S/D electrodes, thermally evaporated Al was used and patterned using a lithography process. Finally, contact annealing was carried out at 300 °C for 30 minutes in N₂. Results and discussion Figure 2(a) shows the I D-V D characteristics of the fabricated n-TFT with the updated dumbbell-shaped channel while Figure 2(b) shows the I D-V G transfer characteristics of both the conventional rectangular channel and the updated dumbbell-shaped channel. By comparing the I D-V G with those two types of channel shapes, we observe that channel shrinking has a preferable effect on improving the ON/OFF ratio, particularly by reducing the OFF-state current.To further investigate this effect, we examined the relationship between the ON/OFF ratio and channel width reduction. Figure 3 illustrates the I D-V G trend with different channel widths. The results indicate that while the ON-state current remains relatively stable as the channel width decreases, the OFF-state current significantly declines with channel width reduction. Additionally, we compared the electrical performance of the dumbbell-shaped channel and a narrow channel with the same width, as shown in Figure 4. The comparison reveals a substantial reduction in OFF-state current while maintaining a highly consistent ON-state current. This significant reduction in OFF current may be attributed to several factors. One possible reason is the decrease in grain boundaries within the channel region, which helps suppress leakage current in the OFF state. Another potential factor is improved channel controllability by the gate voltage. Previous studies have reported that shrinking the channel width can reduce leakage current at the back interface of the semiconductor thin film due to the edge effect [6,7]. Although further studies are required, these findings suggest that TFT performance can be enhanced by reducing the channel width and increasing the number of channels. Acknowledgements This work was partially supported by NEDO unreached challenge 2050 (P14004), JST-SPRING (JPMJSP2136), JST-ASPIRE, and the Cooperative Research Project of RIEC No. R06/A06, Tohoku University. The ion implantation was conducted at the CMS, Kyushu Institute of Technology.

This chapter gives a brief overview of different aspects of defects in crystalline silicon. It discusses the structural aspects of lattice defects and focuses on their electronic properties. It illustrates the defect generation and behaviour during integrated circuit processes, and also includes a short discussion on the impact of crystallographic defects on the electrical device performance. The number of intrinsic point defects in thermal equilibrium depends on the temperature and on their formation energy and can be estimated using basic statistical physics. The solubility of intrinsic point defects is less well known than that of extrinsic point defects as it is only accessible through indirect experiments. The Burgers vector can be obtained by drawing a Burgers circuit which is any closed loop around a dislocation going from atom to atom. Plastic deformation of silicon requires the presence of large numbers of dislocations.

Transistor gate patterning is the primary application of a high-resolution lithographic system in the semiconductor industry. The gate itself is typically a long, narrow line of polysilicon whose width (known as the transistor gate “length”) determines the device switching speed. The uniformity of the gate is critical for device electrical performance and yield. Gate patterning is performed after significant device processing. Therefore the feature must be accurately aligned to the previously patterned regions. It must also be written over the sample topography created by the prior fabrication steps.KeywordsRapid Thermal AnnealElectron Beam LithographyGate LengthShallow Trench IsolationEffective Channel LengthThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

New dispersion model for band gap tracking

In this paper we present a novel process based on SU-8 technology for the fabrication of double clamped RF MEMS capacitive shunt switches in coplanar configuration. The key element of the exploited process is the MicroChem SU-8 2002 negative photoresist. The polymeric material is widely used in MEMS device processes because of its excellent thermal and chemical stability. In this paper, SU-8 polymer has been utilized in a double way to get suspended structures as double clamped beams: (i) SU-8 for the lateral supports, and (ii) as a sacrificial layer for the release of the suspended membrane. Preliminary RF tests on the manufactured switches have been done, and the measured electrical performances are in good agreement with the performed simulations.