Delay and area optimization for discrete gate sizes under double-sided timing constraints

Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power and area optimization. However, finding the optimal gate sizing solution is NP-hard [1], and the suboptimality of sizing solutions has not been sufficiently quantified for each heuristic. Thus, the need for further research has been unclear. In this work, we describe a new benchmark generation approach for leakage power-driven gate sizing (the subject of the forthcoming ISPD-2012 contest) which constructs realistic circuit netlists with known optimal solutions. The generated netlists resemble real designs in terms of gate count, maximum path depth, interconnect complexity (Rent parameter), and net degree distributions. Using these benchmark circuits with known optimal gate size, we have studied the suboptimality of several leakage-driven gate sizing heuristics, including two commercial tools, with respect to key circuit topology parameters. Our study shows that common sizing methods are suboptimal for realistic benchmark circuits by up to 52.2% and 43.7% for V t-assignment and gate sizing formulations, respectively. The results also suggest that (1) commercial tools may still suffer from significant suboptimality, and/or (2) existing methods have "similar" degrees of suboptimality. Copyright 2012 ACM.

In this paper, we first present an efficient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure is embedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As a result, the algorithm is able to obtain superior solutions.

Increasing dominance of process variations in the nanometer designs are posing significant challenges for circuit design and optimization. The variations in parameters such as channel length and the gate oxide thickness impacts circuit delay and power. In this paper, we propose a new gate sizing algorithm using fuzzy mathematical programming (FMP) in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay, which is a function of gate sizes and the fan-outs of the gate, are represented using triangular fuzzy numbers with linear membership functions. The variation aware gate sizing problem is formulated as a fuzzy mathematical program to perform a delay constrained power minimization in the presence of variations. Initially, a deterministic optimization is performed by fixing the fuzzy parameters to the worst and the average case values and the results are used to convert the fuzzy optimization problem into a crisp non-linear problem which is then solved using a non-linear optimization solver. The above model with delay and power as constraints, maximizes the robustness, i.e., the variation resistance of the circuit and thus the yield. The proposed approach was tested on ISCAS '85 benchmarks and the results were validated for timing yield using monte-carlo simulations. The fuzzy approach yields significantly better results compared to stochastic programming based gate sizing approach with a comparable runtime.

: This thesis considers two problems in computer-aided design of VLSI circuits: (1) discrete gate sizing and (2) timing-driven placement improvement. The discrete gate-sizing problem is described as follows. A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient solution algorithm for combinational circuits, we examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit and by adjusting the delays between the central clock distribution node and individual flip-flops. Existing methods treat these two problems separately, which may lead to very suboptimal solutions in some cases. We develop a novel unified approach to tackle them simultaneously. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical perspective. In this paper, we propose a new gate sizing algorithm using fuzzy linear programming in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay which is a function of the gate sizes and the fan-outs of the gates are represented using triangular fuzzy numbers with linear membership functions. Initially, as a preprocessing step for fuzzy optimization, we perform deterministic optimizations by fixing the fuzzy parameters to the worst and the average case values, the results of which are used to convert the fuzzy optimization problem into a crisp nonlinear problem. The crisp problem with delay and power as constraints is then formulated to maximize the robustness, i.e., the variation resistance of the circuit. The fuzzy optimization approach was tested on ITC'99 benchmark circuits and the results were validated for timing yield using Monte Carlo simulations. The proposed approach is shown to achieve better power reduction than the worst case deterministic optimization as well as the stochastic programming based gate sizing methods, while having comparable runtimes.

The crosstalk noise induced on a net depends on its wire size, its driver size and the sizes of the aggressor gates driving its coupled nets. The problem of crosstalk noise optimization at post-route level is difficult due to the cyclic dependency on aggressor and victim driver sizes, resulting in a conflicting situation. Game theory provides a natural framework for handling conflicting objectives and allows simultaneous optimization of multiple parameters. The formulation of a convex objective function is a requirement in order to obtain better optimization in a game theoretic framework. This property is exploited to solve the cyclic dependency of crosstalk noise on its gate and wire sizes, while modeling the problem of simultaneous optimization of interconnect delay and crosstalk noise. A game is modeled with the crosstalk noise and interconnect delay of the chosen net as the players, the possible gate and wire sizes as the strategy set and the analytical expressions for crosstalk noise and interconnect delay as their respective expected payoffs. The time and space complexity of the proposed integrated sizing algorithm is linear in terms of the number of gates and wires in the design. Experimental results on several medium and large open core designs indicate average improvements of 27.52% and 34.03% for interconnect delay and crosstalk noise respectively, achieved by game theoretic gate sizing based on noise criticality over and above the optimization from the Cadence place and route tools without any area overhead or the need for rerouting

The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard logical effort (LE) in the presence of interconnects. The condition for optimal gate sizing in a logic path with long wires is also presented. This condition is achieved when the delay component due to the gate input capacitance is equal to the delay component due to the effective output resistance of the gate. The ULE delay model unifies the problems of gate sizing and repeater insertion: In the case of negligible interconnect, the ULE method converges to standard LE optimization, yielding tapered gate sizes. In the case of long wires, the solution converges toward uniform sizing of gates and repeaters. The technique is applied to various types of logic paths to demonstrate the influence of wire length, gate type, and technology.

The authors are concerned with the optimisation of combinational logic circuits. The competing factors, active area and delay time, are considered in the optimisation. The total active area is assumed to be a linear function of the gate sizes. There is a critical path whose delay time, the longest delay time of the circuit, depends on the sizes of the individual gates. This path will change many times during the optimisation. The optimisation process is used to produce the trade-off curve. The proposed methodology is based on the optimisation of the circuit critical path. This is a gate sizing problem on those paths that define the delay time of a circuit. Given a drive size for all the gates of the circuit, the trade-off curve contains design space points of minimum delay time and active area. A variable-sized subset of the Boolean network is optimised. Only the gates in the circuit critical path are optimised. The gates in the Boolean network which are not in the critical path do not need to be optimised. An efficient method is proposed for updating the critical path as the trade-off curve is obtained. Performance comparison and results were obtained over the set of MCNC two-level and combinational multilevel benchmark circuits. The proposed methodology produces trade-off curves, in relatively large circuits, with a great reduction in number of variables and run-time compared with the original full problem. In the proposed method, the number of variables is reduced by a factor of up to 7.3 times relative to the original full problem. The run-time behaviour is excellent, with an improvement between 1.5 and 32.5 times less CPU time compared with computation of the full Boolean network. With a higher gate count of the circuit, there are greater improvements in both run-time and number of variables.

Standard cell libraries provide designers with a fixed set of well characterized logic blocks. As designs are pushed for high performance, low area, and low power, it is essential to have a, good standard cell library that can help achieve these goals. As gate sizing is crucial to timing, the number of gate sizes (drive strengths) available for each of the primitives is an important factor to be considered. While an infinite granularity of gate sizes is preferable to get the best entitlement, it is often impractical due to the huge cost associated with developing and maintaining libraries. It is therefore essential to find ways to achieve the best performance, power and area, with a, reasonable library size. In this paper we focus on the problem of finding out the optimal ratio of gate sizes to be selected. 65nm libraries were used for validating the claims on a real design and the results are presented in this paper

Recent work has established Lagrangian relaxation (LR) based gate sizing as state-of-the-art providing the best power reduction with low run time. Gate sizing has limited potential to reduce the power when the timing constraints are tight. By adjusting the arrival times of clock signals (clock skew scheduling), the timing constraints can be relaxed facilitating more power reduction.Previous LR attempts at simultaneous gate sizing and skew scheduling solved a minimum-cost network flow problem for updating the Lagrange multipliers in each LR iteration, and for optimality assumed continuous sizes with convex delay models. We propose an alternative approach, modifying a LR discrete gate sizing formulation with table lookup non-convex delay models, which are more accurate for modern process technologies. For the Lagrange multiplier update, we use a projection heuristic that is much faster than solving the minimum cost network flow problem.On the ISPD 2012 gate sizing contest benchmark suite, our proposed approach outperforms the previous min-cost flow based approach by saving 5.3% more power and is 70x faster. Compared to sizing alone with the state-of-the-art LR gate sizer, skew scheduling with sizing saves 19.7% more power with a small runtime penalty.

In a typical circuit optimization flow, one essential decision is to select the implementation for each gate according to a cell library. An implementation implies specific gate size, threshold voltage, etc. The selection normally needs to handle multiple and often conflicting objectives. An effective approach for multi-objective optimization is Lagrangian relaxation (LR), which has been adopted in continuous gate sizing. When LR is applied to the gate implementation selection, the Lagrangian dual problem is no longer convex like in continuous gate sizing, and conventional sub-gradient method becomes inefficient. In this paper, we propose a projection-based descent method and a new technique of Lagrangian multiplier distribution for solving the Lagrangian dual problem in discrete space. Experimental results demonstrate that our approach leads to significantly better solution quality and faster convergence compared to the sub-gradient method.

In this paper, we propose a timing-aware power-noise reduction technique. Our approach consists of prediction and correction steps. Before placement, we estimate the power noise of each cell considering switching frequency of cells which, after placement, will most likely be in the neighborhood. If a frequently switching cell has neighbors which switch infrequently, it is unlikely that this cell will suffer from a power noise problem. Based on the cell power noise estimation, we add decap padding to each cell. Then we invoke a standard cell placement tool and perform power grid analysis. We eliminate the power grid noise by gate sizing. Our technique can reallocate decaps to improve power noise, power consumption, and timing. The gate sizing is based on the sequence of linear programs (SLP) formulation, and it can be solved efficiently. Experimental results show that our techniques can effectively reduce power noise and meet timing constraints.

The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including Vt and Lg. Within the research-oriented infrastructure used in the ISPD 2012 Gate Sizing Contest, we develop a metaheuristic approach to gate sizing that integrates timing and power optimization, and handles several types of constraints. Our solutions are evaluated using a rigorous protocol that computes circuit delay with Synopsys PrimeTime. Our implementation Trident outperforms the best-reported results on all but one of the ISPD 2012 benchmarks. Compared to the 2012 contest winner, we further reduce leakage power by an average of 43%.

In this article, we derive a simple and accurate expression for the change in timing yield due to a change in the gate delay distribution. It is based on analytical bounds that we have derived for the moments of the circuit and path delay. Based on this, we propose computationally efficient algorithms for (1) discrete gate sizing and (2) simultaneous gate sizing and threshold voltage ( V T ) assignment so that the circuit meets a timing yield specification under parameter variations. The use of this analytical yield gradient within a gradient-based timing yield optimization algorithm results in a significant improvement in the runtime as compared to the numerical method, while achieving the same final yield. It also allows us to explore a larger search space in each iteration more efficiently, which is required in the case of simultaneous resizing and V T assignment. We also propose heuristics for resizing/changing the V T of multiple gates in each iteration. This makes it possible to optimize the timing yield for large circuits. Results on ITC ’99 benchmarks show that the proposed multinode resizing algorithm results in a significant improvement in the runtime with a marginal average area penalty and no cost to the final yield achieved.

Previous article Next article Complementarity Theorems for Linear ProgrammingA. C. WilliamsA. C. Williamshttps://doi.org/10.1137/1012015PDFBibTexSections ToolsAdd to favoritesExport CitationTrack CitationsEmail SectionsAbout[1] Frank Eugene Clark, Mathematical Notes: Remark on the Constraint Sets in Linear Programming, Amer. Math. Monthly, 68 (1961), 351–352 MR1531192 0109.38204 CrossrefISIGoogle Scholar[2] A. J. Goldman, Resolution and separation theorems for polyhedral convex setsLinear inequalities and related systems, Annals of Mathematics Studies, no. 38, Princeton University Press, Princeton, N. J., 1956, 41–51, in [4] MR0089113 0072.37505 Google Scholar[3] A. J. Goldman and , A. W. Tucker, Theory of linear programmingLinear inequalities and related systems, Annals of Mathematics Studies, no. 38, Princeton University Press, Princeton, N.J., 1956, 53–97, in [4] MR0101826 0072.37601 Google Scholar[4] H. W. Kuhn and , A. W. Tucker, Linear Inequalities and Related Systems, Princeton University Press, Princeton, 1956 0072.37502 Google Scholar[5] A. C. Williams, Boundedness relations for linear constraint sets, Linear Algebra and Appl., 3 (1970), 129–141 10.1016/0024-3795(70)90009-1 MR0266612 0201.22003 CrossrefGoogle Scholar Previous article Next article FiguresRelatedReferencesCited byDetails Sparse solutions to an underdetermined system of linear equations via penalized Huber loss6 November 2020 | Optimization and Engineering, Vol. 22, No. 3 Cross Ref Dynamic Non-diagonal Regularization in Interior Point Methods for Linear and Convex Quadratic Programming26 February 2019 | Journal of Optimization Theory and Applications, Vol. 181, No. 3 Cross Ref Necessary and Sufficient Conditions for Noiseless Sparse Recovery via Convex Quadratic SplinesMustafa Ç Pinar12 February 2019 | SIAM Journal on Matrix Analysis and Applications, Vol. 40, No. 1AbstractPDF (416 KB)A labeling algorithm for the sensitivity ranges of the assignment problemApplied Mathematical Modelling, Vol. 35, No. 10 Cross Ref Bibliography15 August 2011 Cross Ref Sensitivity Analysis and Dynamic Programming15 February 2011 Cross Ref Bibliography Cross Ref Condition measures and properties of the central trajectory of a linear programMathematical Programming, Vol. 83, No. 1-3 Cross Ref New characterizations of ℓ1 solutions to overdetermined systems of linear equationsOperations Research Letters, Vol. 16, No. 3 Cross Ref Limiting behavior of weighted central paths in linear programmingMathematical Programming, Vol. 65, No. 1-3 Cross Ref Stability of linearly constrained convex quadratic programsJournal of Optimization Theory and Applications, Vol. 64, No. 1 Cross Ref Marginal values in mixed integer linear programmingMathematical Programming, Vol. 44, No. 1-3 Cross Ref A theory of linear inequality systemsLinear Algebra and its Applications, Vol. 106 Cross Ref Boundedness relations in linear semi-infinite programmingAdvances in Applied Mathematics, Vol. 8, No. 1 Cross Ref A Variable-Complexity Norm Maximization ProblemO. L. Mangasarian and T. -H. Shiau17 July 2006 | SIAM Journal on Algebraic Discrete Methods, Vol. 7, No. 3AbstractPDF (698 KB)Simple computable bounds for solutions of linear complementarity problems and linear programs26 February 2009 Cross Ref On polyhedral extension of some LP theoremsMathematical Programming, Vol. 30, No. 1 Cross Ref Polyhedral extensions of some theorems of linear programmingMathematical Programming, Vol. 24, No. 1 Cross Ref Optimal simplex tableau characterization of unique and bounded solutions of linear programsJournal of Optimization Theory and Applications, Vol. 35, No. 1 Cross Ref Projection and Restriction Methods in Geometric Programming and Related Problems Cross Ref Representation of Convex Sets Cross Ref Projection and restriction methods in geometric programming and related problemsJournal of Optimization Theory and Applications, Vol. 26, No. 1 Cross Ref The complementary unboundedness of dual feasible solution sets in convex programmingMathematical Programming, Vol. 12, No. 1 Cross Ref Theorems on the dimension of convex setsLinear Algebra and its Applications, Vol. 12, No. 1 Cross Ref On the primal and dual constraint sets in geometric programmingJournal of Mathematical Analysis and Applications, Vol. 32, No. 3 Cross Ref Volume 12, Issue 1| 1970SIAM Review History Submitted:23 December 1968Published online:18 July 2006 InformationCopyright © 1970 Society for Industrial and Applied MathematicsPDF Download Article & Publication DataArticle DOI:10.1137/1012015Article page range:pp. 135-137ISSN (print):0036-1445ISSN (online):1095-7200Publisher:Society for Industrial and Applied Mathematics