Delay and power consumption estimation in embedded systems using hierarchical performance modeling

With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to ${3.6 \times }$ runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy.

International audience

In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a floorplan-based power and clock distribution methodology for ASIC design. From the floorplan and the estimated power consumption, the power network size is determined at an early design stage. Next, without detailed gate-level net list , clock interconnect sizing, the number and strength of clock buffers are planned for balanced clock distribution. This early planning methodology at the full-chip level enables us to fix the global interconnect issues before the detailed layout composition is started.

Power analysis is an important and efficient mean for side channel attacks on security applications. By monitoring devices' power consumption during various operations it is possible to collect security information (e.g. the encryption key). These power drop-offs counter effects could be reduced or even eliminated, if accurate power estimations could be achieved on the early design cycles. It is crucial for the designers, to be able to evaluate accurately the power consumption during the development process, especially for the widely used, power consuming, security algorithms. This paper presents and compares the estimated and measured power consumption of security algorithms on both Xilinx and Altera FPGAs. The estimation numbers are produced using each vendor's commercial power estimation tool.The differences between measured and estimated power consumption, varied from 15.52% to 208% for the Xilinx devices and from 5.64% to 32.15% for the Altera device.As a result, although Altera's PowerPlay power estimation tool gene/rated more accurate results than Xilinx's Xpower tool, none of them seems to be yet mature enough for the very demanding security era.

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Triple Modular redundancy technique is mostly used to mask transient faults in circuits operating in dependable systems. The generalization of this technique (known as nMR) allows the use of more than three redundant copies of the circuit to increase the reliability under multiple faults. The main drawback of nMR is its high power consumption, which usually implies in n times the power consumption of a single circuit. In this work, we present a mathematical model that predicts the power consumption overhead based on the power characteristics of the basic module. We estimate power consumption in some case-study circuits protected by nMR in a commercial SRAM-based FPGA and compare to a proposed model that estimates power consumption penalty. Results demonstrate that nMR can be implemented with low power overhead in FPGAs and therefore it is a suitable technique for most applications synthesized into this type of programmable devices that need to cope with massive multiple faults.

Several reports showed that the most important issue in smartphones was its power consumption. For saving power consumption, estimating power is important. The power consumption of each application depends on other applications installed in the device. In this paper, we propose a method for estimating power consumption of each application considering this software dependency. We then evaluate the method with intermittently invoked applications and show that the method can estimate power consumption accurately.

In the paper, a methodology of power conscious RTL test scheduling is described. The methodology is based on the fact that circuit under analysis (CUA) is partitioned into testable blocks (TB), the information about the partitioning is the input information for the methodology. TBs are mapped into AMI platform, for each TB the sequences of test vectors are then derived, a professional tool is used for this purpose. The sequences of test vectors are then reordered with the goal to reduce power consumption during test application by reducing switching activities. The power consumption estimation is combined with the implemented platform which allows to gain more precise results. The values of TBs power consumption are then used in RTL test scheduling methodology. The goal is to find test schedule with lowest test application time and lower power consumption than the required maximal value.

Data centers as a cost-effective infrastructure for hosting Cloud and Grid applications incur tremendous energy cost and C02 emissions in terms of power distribution and cooling. One of the effective approaches for saving energy in a cluster environment is workload consolidation. However, it is challenging to address this schedule problem as it requires the understanding of various cost factors. One of the important factors is the estimation of power consumption. Power models used in most of workload schedule solutions are a linear function of resource features, but we analysed the measurement data from our cluster and found the resource loads, in particular I/O load, had no convincing linear-correlation with power consumption. Based on measurement data sets from our cluster, we propose multiple non-linear machine learning approaches to estimate power consumption of an entire node using OS-reported resource features. We evaluate the accuracy, portability and usability of the linear and non-linear approaches. Our work shows the multiple-variable linear regression approach is more precise than the CPU only linear approach. The neural network approaches have a slight advantage - its mean root mean square error is at most 15% less than that of the multiple-variable linear approach. But the neural network models have worse portability when the models generated on a node are applied on its homogeneous nodes. Gaussian Mixture Model has the highest accuracy on Hadoop nodes but requires the longest training time.

In this chapter, a cycle approximate simulator for multi-processor system-on chip is presented. The aim of this simulation tool is to enable an enhanced software/hardware analysis capability for bus based systems. The most important contributions are represented by its high flexibility (easy configuration of a SoC using dedicated libraries for generic and specific components and easy integration of other simulators and models), accurate modeling of features specific to multiprocessor systems (busses, inter processor communication mechanisms, etc), accurate implementation of a wide range of performance metrics and power consumption estimates (for processors that support this) and high simulation speed. This way, the proposed simulator can be used for both hardware architecture design exploration and software development.

As the latest international video coding standard, H.264 is gaining importance not only on desktop computers but also on handheld devices. For handheld devices, power consumption of the system is of ultimate importance, which needs to be addressed at every layer of the system design. At the application layer, the code size affects the memory hierarchy behavior, which in turn affects the system power performance. In this paper, we consider the power consumption of H.264 running on handheld devices using multicore DSP processors, focusing particularly on power saving through code reduction. We use the multiple intra-mode prediction as an example. There are nine optional prediction modes for each 4 times 4 intra luma sub-macroblock in H.264, which result in nine separate routines. We examine the access patterns of the modes and propose a general scheme that replaces eight of the nine routines with one. This dramatically reduces the code size and the resultant power consumption. We implemented the code on PACDSP, resulting in a 20% reduction of the code size with negligible performance degradation.

<div class="htmlview paragraph">As the complexity of automotive embedded software grows, it is desirable to bring as much automation into the development process as possible, as evidenced by efficient code generators from modeling tools such as Simulink. However, the current development process does not pay enough attention to non-functional issues such as real-time requirements. Modeling tools such as Simulink do not allow representation of the target platform, so it is not possible to analyze real-time behavior in the early design stage. The typical approach is to download the executable to the target micro-controller and measure to see if there are any missed deadlines. We describe a tool that can be used to model system-level software and hardware architectures and analyze system timing behavior at early design stages, and assess the impact of the target platform on control system performance.</div>

SummaryPower consumption of current High Performance Computing systems has to be reduced by at least one order of magnitude before they can be scaled up towards ExaFLOP performance. While we can expect novel hardware technologies and architectures to contribute towards this goal, significant advances have to come also from software technologies such as proactive and power‐aware scheduling, resource allocation, and fault‐tolerant computing. Development of these software technologies in turn relies heavily on our ability to model and accurately predict power consumption in large computing systems. In this paper, we present a data‐driven model of power consumption for a hybrid supercomputer (which held the top spot in the Green500 ranking in June 2013) that combines CPU, GPU, and MIC technologies to achieve high levels of energy efficiency. Our model takes as input workload characteristics—the number and location of resources that are used by each job at a certain time—and calculates a predicted power consumption at the system level. The model is application‐code‐agnostic and is based solely on a data‐driven predictive approach, where log data describing the past jobs in the system are employed to estimate future power consumption. For this, three different model components are developed and integrated. The first employs support vector regression to predict power usage for jobs before these are started. The second uses a simple heuristic to predict the length of jobs, again before they start. The two predictions are then combined to estimate power consumption due to the job at all computational elements in the system. The third component is a linear model that takes as input the power consumption at the computing units and predicts system‐wide power consumption. Our method achieves highly‐accurate predictions starting solely from workload information and user histories. The model can be applied to power‐aware scheduling and power capping: alternative workload dispatching configurations can be evaluated from a power perspective and more efficient ones can be selected. The methodology outlined here can be easily adapted to other HPC systems where the same types of log data are available.

Nowadays a system level estimation method of power consumption for heterogeneous systems is a major concern. In this article, we introduce an empirical method for power consumption modeling of analog components at system level. The principal step of this method uses neural networks to approximate the mathematical curve of the power consumption as a function of the inputs, supply voltage and ambient temperature of an analog component. For an amplifier, we found an average error of 4.72% between our high level estimation and PSPICE power consumption results. This novel method is suitable for IP-based design and has three key features. Firstly, the method provides an online estimation of the instantaneous power consumption of analog blocks. Secondly, the method is generic as it can be applied to any analog component in any modeling and simulation environment. Thirdly, the method is suitable for the total (analog and digital) power consumption estimation of a heterogeneous system.