Delay approximation for nanomagnetic logic based combinatorial circuits

Among the new technologies that have emerged in the past few years to address the limits of CMOS, Nanomagnetic Logic (NML) is one of the most promising. NML circuits are composed of nanosized elongated magnets that operate at room temperature with ultra-low switching power dissipation. To create an NML circuit, the designer must place the magnets in such a way that, through magnetostatic interactions, signal propagation and logic are accomplished. The design of large NML circuits is at its infancy, where case studies involving complex circuits are lacking. To bridge this gap, we have examined two study cases: a Content Addressable Memory (CAM) and its ternary variant called Ternary Content Addressable Memory (TCAM). CAM/TCAM differ from traditional RAM as the input is a data word instead of a memory address. CAM/TCAM provides the position where a given word can be found. In this paper, we present an overview of the functionality of NML, the proposed architectures, and its basic building blocks. We simulated the designs and showed that the memories work as expected. This work shows a potential tool for NML components design.

With the approaching of CMOS scaling limits the interest on emerging technologies is rapidly growing. Among emerging technologies, Quantum dot Cellular Automata (QCA) is one of the most studied. Particularly the magnetic implementation, NanoMagnet Logic (NML), offers very low power consumption and it combines logic and memory on a unique device. Despite the advantages of these technologies, QCA and NML working principle relies on the electric or magnetic interaction among neighbor cells, so it is very sensitive to process variations. The behavior of circuits is therefore largely affected by defects and fabrication variations. To effectively design circuits with these technologies, proper tools for testing circuits are necessary. In this work we present an innovative test environment for NML technology. The test algorithm is integrated in ToPoliNano, our design and simulation tool for emerging technologies, and it is specifically tailored to support the analysis of faults in large complexity circuits. Thanks to this tool it is possible to design and test complex NML circuits considering the effect of process variations in terms of Yield and Output Error Rate. The approach gives then feedback to the technologists, remarkably helping the future development of this technology. Moreover, notwithstanding the methodology is applied here to NML circuits only, it can also be successfully applied to QCA technology in general, greatly enhancing the value of the work we proposed here.

Nanomagnetic logic (NML) is a promising candidate for the real implementation of quantum-dot cellular automata circuits and can be a proper alternative or complement to CMOS circuits. Like any other nanoscale technologies, NML circuits are also subject to fabrication variations. These variations along with fluctuations caused by thermal noise can affect the performance of these circuits. Therefore, design of NML circuits with high testability is an absolute necessity. Circuits based on conservative logic are inherently testable because of their specific properties. In this paper, considering the physical and geometrical properties of nanomagnets, a nanomagnetic conservative quantum-dot cellular automata gate is designed and evaluated. This circuit can be used as the basic block for the realization of more complex conservative NML circuits. To implement this circuit, the design of the clocked nanomagnetic majority gate is also provided. The OOMMF physical simulation tool is used for simulation and evaluation. The results show the correct functionality of the proposed conservative gate at room temperature. It operates about 34% faster than the NML Fredkin gate. Moreover, the NML version of the conventional Fredkin gate takes 90% more area than the proposed design.

We consider the design of stochastic computing (SC) hardware based on spintronic devices. SC offers low-cost implementations of arithmetic operations and high degrees of error tolerance. When compared to charge-based devices, spin-based devices could be lower energy, nonvolatile, etc. However, spin-based devices can be fundamentally more error prone than charge-based devices. The marriage of SC architectures and spin-based devices has the potential to produce information processing systems that are robust, low energy, and nonvolatile. In this paper, we investigate SC hardware comprised of nanomagnetic logic (NML) devices. NML is a “beyond-CMOS” technology that uses bistable magnets to store, process, and move binary information. We introduce new NML circuit structures that exploit unique features of the technology to efficiently realize hardware components required for an SC system (e.g., random number generation). We also benchmark NML-based SC circuits against other implementations, and illustrate how features that are unique to NML (e.g., inherent pipelining) can lead to improved performance. Our results indicate NML SC implementations achieve smaller area footprints with reduced energy and delay when compared to CMOS equivalents.

Among emerging technologies Quantum dot Cellular Automata (QCA) plays a fundamental role. Its magnetic version, normally called NanoMagnet Logic (NML), is particularly interesting thanks to the ability to work at room temperature and to mix logic and memory in the same device. Magnetic circuits have also a potential very low power consumption. Unfortunately classic NML circuits are normally driven (clocked) with a current generating a clocked magnetic field, nullifying the possibility to actually obtain low power circuits. We have recently developed a technology-friendly solution, the MagnetoElastic NML (ME-NML), where magnetic circuits are driven through an electric field, and not with a current, drastically reducing the power consumption. In this paper we start to explore the architectural consequences of this new magnetic technology. The analysis is performed using as a benchmark a Galois multiplier, a systolic architecture particularly suited for QCA and NML technologies. The layout is precisely described and the resulting circuit is modeled and simulated using VHDL language. The obtained results are remarkable. The circuit area is reduced by 4 times compared to classic NML approach. This, coupled with the intrinsic lower power consumption due to different clock, leads to a 50 times reduction of power absorption. Moreover the particular structure of magnetoelastic NML allows to define a library of standard cells that can be easily used by designers and automatic layout tools to design circuits, greatly improving future research in this field.

We discuss the experimental demonstration of non-majority, two-input, nanomagnet logic(NML) AND and OR gates. While gate designs still can incorporate the symmetric,rounded-rectangle magnets used in the three-input majority gate experiments by Imre(2006 Science 311 205–8), our new designs also leverage magnets with an edge that has awell-defined ‘slant’. In rectangular and ellipsoid nanomagnets, the easy axis of the devicecoincides with its longer edge. For a magnet with a slanted edge, the easy and hard axesare ‘tilted’, and magnetic fields applied along the (geometrical) hard axis alone can set theeasy axis magnetization state. This switching phenomenon can be employed to realizeNML Boolean logic gates with both reduced footprints and critical path delays.Experimental demonstrations of two-input AND and OR gates are supported bycorresponding micromagnetic simulations with temperature effects associated with a 300 Kenvironment. Simulations suggest that the time evolution of experimentally demonstratedstructures is correct, and that designs can also tolerate clock field misalignment.Additionally, simulations suggest that a slanted-edge ‘compute magnet’ can (i) be drivenby two anti-ferromagnetically ordered lines of NML devices (for input) and (ii)drive an anti-ferromagnetically ordered line (for output). Both are essential ifslanted-edge devices are to be used in NML circuits. We conclude with a discussion ofextensibility and scaling prospects for shape-based computation with nanomagnets.

To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Float ing-gate MOS (FGMOS) is one of those techniques and has previously shown poten tially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transis tors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.KeywordsPropagation DelayVery Large Scale IntegrationReduce Power ConsumptionCMOS CircuitSubthreshold RegionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Nanomagnetic logic has the advantages in low power, non-volatility, and room temperature operation, however, low power on-chip clocking is the requirement of its integration. An on-chip clocking structure for a nanomagnetic logic circuit using exchange interaction is proposed in this work. This scheme is to use the Oersted field generated by current-carrying copper wire to magnetize ferromagnetic film cladding and then to switch the magnetization orientation of nanomagnets by the exchange interaction between magnetic layers. Simulation results demonstrate that the proposed scheme can reduce the power dissipation by 5/6 and the marginal spray field by 2/3 compared with the ferromagnetic yoked clocking that uses the external field to switch the magnetization. Therefore, it can reduce the power consumption and the risk of crosstalk. In addition, micromagnetic simulation verifies that nanomagnetic array laid on the proposed clocking can work functionally.

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.

This paper discusses power consumption in the full adder circuit using some fabrication technologies. Though many studies related to power consumption in the full adder circuit were performed, however, few investigations about the effect of the number of bits on the power consumption are addressed. In this paper, the effect of changing the number of bits on the power consumption and time delay of the full adder circuit will be observed and the effect of changing the technology size is going to be calculated. The results will show that there is a direct relationship between the number of bits and power.

This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Nowadays, the intense research effort is focused on exploring alternative emerging device to perform binary logical function. A promising device technology is multiferroic nanomagnet logic. The main reason for the interest in this nanomagnetic switch is its nonvolatility and comparatively low power consumption in combination with the ability to perform logic and storage in one single element. The basic element of multiferroic nanomagnet logic is a sub-100 nm size single domain magnet. Usually, the x-y direction defines the in-plane dimension, while the z axis direction depicts the thickness of nanomagnet. The in-plane magnetizations along easy axis are used to encode binary logic states 1 and 0, respectively; while along the hard axis they denote null logic. The logic operation and data transmission in magnetic logic are realized by the dipole-coupled magnetostatic interactions. In multiferroic nanomagnet logic, the interconnect wire is a very important component since it forms data transmission channel of any nanomagnetic logic circuit. There are two kinds of interconnected wires in this technology, namely antiferromagnetic coupling interconnected wire and ferromagnetic coupling interconnected wire. In this paper, the switching dynamics of a multiferroically and nanomagnetically interconnected wire employing ferromagnetic coupling is simulated by solving the Landau-Lifshitz-Gilbert equation with neglecting the thermal fluctuation effects. The wires are implemented with dipole-coupled two-phase (magnetostrictive/piezoelectric) multiferroic elements that are clocked with electrostatic potentials of 100 mV applied to the piezoelectric layer generating 20 MPa stress in the magnetostrictive layers for switching. Specifically, the ferromagnetic coupling effect model for multiferroic nanomagnet interconnected wire is established, and its magnetization dynamics is simulated by using different stress clocking. It is found that moderate strain (19.7-20.1 MPa) can ensure~180 magnetization reversal, and the logic state is successfully transferred in the ferromagnetic coupling interconnected wire. It is also found that the strong ferromagnetic coupling between multiferroic nanomagnets blocks effective magnetization reversal. This may arise from small spacing-induced out-of-plane magnetization, which does not favor the in-plane magnetization. These findings can provide some guidance for multiferroic logic circuit design.

As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss. Considering the situations, variationaware designs for yield enhancement interest researchers. This paper investigates to exploit the statistical features in circuit delay and to cascade dependent instructions for reducing variations. From statistical static timing analysis in circuit level and performance evaluation in processor level, this paper tries to unveil how efficiently instruction cascading improves performance yield of processors. Cascading instructions increases logic depth and decreases the standard deviation of the circuit delay. That might improve performance yield of microprocessors. Unfortunately, however, it is found that variability reduction in the circuit level does not always mean yield enhancement in the microarchitecture level.

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

If a test set exists for a CMOS circuit which detects all the stuck-open faults in it in the presence of arbitrary circuit delays and timing skews, then the circuit is said to be robustly testable. We saw earlier in Chapter 2 that dynamic CMOS circuits, such as domino CMOS and cascode voltage switch logic circuits, are always robustly testable. However, this is not true for all static CMOS circuits. In this chapter, procedures for designing robustly testable static CMOS circuits will be discussed. Generally, the circuits are designed to be robustly testable with respect to single stuck-open faults. However, we will also discuss a method which guarantees robust testability with respect to multiple faults.KeywordsTest VectorpMOS TransistorCMOS CircuitNAND GateDelay FaultThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.