Transistor size optimization in the tailor layout system

This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e., the delay of long paths are shortened and the delay of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which are caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay.

Dynamic logic is susceptible to noise, especially in the ultra-deep submicrometer dual threshold voltage technology. When the dual threshold voltage is applied to the domino logic, noise immunity must be carefully considered since the significant subthreshold current of the low threshold voltage transistor makes the dynamic node much more susceptible to noise. In the first part of this paper, we introduce a new keeper transistor sizing method to determine the optimal keeper transistor size in terms of speed, power, and noise immunity. With the use of data obtained by presimulation, it is unnecessary to simulate all the design corners corresponding to the feasible NMOS evaluation transistor size ranges to find the optimal keeper transistor size. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all the domino logic gates. In the second part of this paper, we propose a new dual threshold voltage domino logic synthesis with the keeper transistor sizing to minimize the power consumption while meeting delay and noise constraints. With the optimal keeper transistor size determined by the proposed keeper transistor sizing method, the dual threshold voltage assignment to domino logic can be simplified to the discrete threshold voltage selection. Experimental results for ISCAS85 benchmark circuits show significant savings on leakage power and active power.

For certain high speed CMOS circuits, e.g. clock drivers, wave-pipelined circuits, it is very important to limit the spread in circuit delay as well as the worst-case delay. The delay spread or skew, is caused by the data-dependency of the circuit delay. To reduce the effect of process and environmental variations on skew and circuit delay, the transistors in a CMOS circuit need to be carefully sized. In this paper, we present a stochastic optimization approach to transistor sizing. Each sizing scheme considered during optimization is evaluated through accurate circuit simulations to determine the delay and skew values. The power of the optimization technique enables us to generate very good siting schemes with few simulations, as demonstrated by the example given here.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 2400-transistor circuit, and succeeded in reducing the transistor count by 12%, and the net count by 13%. Transistor sizing and layout compaction reduced the average transistor size by one eighth, while the same delay was maintained. Power dissipation was cut to less than half, even when wiring capacitances were dominant.

Voltage-drop is a well-known signal integrity issue in very deep submicron technology. Voltage drop does not only induce circuit delay, but also reduces the circuit noise margins from lower supply voltages and creates reliability issues from electromigration. Voltage drop occurs due to the insufficient current supplied under design circuit state transitions. In this paper, a maximum transition current computation tool is developed. The proposed PIPD is a gate level path delay analysis tool used under insufficient current supplied conditions. This tool could help designers to quickly compute/estimate the longest path delay when voltage drop issues occur. With regard to this research issue, past works are pattern independent, which are worst-case assumptions. PIPD use a real functional test bench to activate gate transitions' peak current. The circuit peak current being accurate estimated in this research, which confirmed that dynamic behavior is pattern dependent. The proposed pattern dependent method is more realistic, and the measurement results might be lower and more accurate than earlier works. Using a PIPD could help design reasonable power rails. The simulation results prove that PIPD gate-level computation results are very close to the HSPICE transistor-level simulation results, with the average differing ratios being less than 8%, while the computation speed is increased 10X. Different to conventional EDA tools, PIPD also found that voltage drop is not certain to impact circuit delay times and calibrated by several real designed circuits.

The fabrication of fine-dimension silicon-gate MOS devices on both silicon-on-sapphire and bulk-silicon substrates has made possible a direct comparison of the electrical characteristics of devices based on these technologies. The same CMOS test chip design was used in both cases and provided both n- and p-channel devices having gate dimensions ranging down to submicrometer levels. Extensive electrical evaluation of the resulting devices has enabled quantitative comparison of carrier mobilities, short- and narrow-channel threshold voltage shifts, punchthrough, and subthreshold characteristics for SOS and bulk-silicon technologies. The effect of epitaxial film thickness on these properties for SOS devices is also discussed. An anomalous narrow-channel threshold voltage shift effect is observed in SOS devices and explained in terms of parasitic device characteristics. The general conclusion based on the observations made is that short-and narow-channel effects in SOS devices are significantly less of a problem than in bulk silicon devices at these gate dimensions. The direct comparison of the dynamic performance of SOS and bulk CMOS circuits can be obscured, for example by differences in gate oxide thickness and threshold voltages. In this case, however, both gate oxide thickness and threshold voltages have been closely matched. This, together with the fact that the circuits were fabricated by the same processing facility using the same chip design, should increase the reliability of any comparison. The results have indicated that at 1-µm dimensions the propagation delay of SOS CMOS circuits is 60 percent lower than that of equivalent bulk-silicon CMOS circuits.

Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven partitioning methods based on iterated net reweighting, partitioning, and timing analysis have been proposed (Ababei et al., 2002), as well as methods that apply degrees of freedom such as retiming (Cong et al., 2000), (Cong et al., 2002). In this paper, we identify and validate a simple approach to timing-driven partitioning based on the concept of "V-shaped nodes." We observe that the presence of V-shaped nodes can badly impact circuit performance, as measured by maximum hopcount across the cutline or similar path delay criteria. We extend traditional the Fiduccia-Mattheyses (FM) variant of the Kernighan-Lin (Kernighan and Lin, 1970) algorithm approaches to directly eliminate or minimize "distance-k V-shaped nodes" in the bipartitioning solution, achieving an attractive tradeoff between cutsize and path delay. Experiments show that in comparison to MLPart (Caldwell et al., 2000), our method can reduce the maximum hopcount by 39% while only slightly increasing cutsize and runtime. No previous method improves path delay in such a transparent manner. The new partitioner is incorporated into a placer (http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Placement/Capo/) and circuit delay is evaluated by a commercial static timing analyzer (http://www.ece.uci.edu/eceware/cadence/spl I.bar/docs/pearluser/). The empirical results show that the delay is significantly reduced, at the cost of very acceptable impacts on wirelength and runtime.

If a test set exists for a CMOS circuit which detects all the stuck-open faults in it in the presence of arbitrary circuit delays and timing skews, then the circuit is said to be robustly testable. We saw earlier in Chapter 2 that dynamic CMOS circuits, such as domino CMOS and cascode voltage switch logic circuits, are always robustly testable. However, this is not true for all static CMOS circuits. In this chapter, procedures for designing robustly testable static CMOS circuits will be discussed. Generally, the circuits are designed to be robustly testable with respect to single stuck-open faults. However, we will also discuss a method which guarantees robust testability with respect to multiple faults.KeywordsTest VectorpMOS TransistorCMOS CircuitNAND GateDelay FaultThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.

This paper addresses the problem of true delay estimation during high level design. The true delay is the delay of the longest sensitizable path in the resulting circuit, as opposed to the topological delay which is the delay of the longest path in the circuit. The existing delay estimation techniques either estimate the topological delay, which may be pessimistic if the longest path is unsensitizable or false, or estimate the true delay using gate-level timing analysis which may be prohibitively expensive. Resource sharing in high level synthesis can create false paths in the circuit implementation. Hence, determining the clock period using topological delay can be unduly conservative, resulting in excessive hardware to meet tight timing specifications. In this paper, we introduce an efficient technique to compute an estimate of the true delay. The proposed technique relies on partitioning the paths in the circuit and topological delay computation, and not on path sensitization. The paths in the implementation are partitioned into two sets given the high level information on scheduling and resource sharing: the complete determining path set (CDP/sub R/) and the nondetermining path set (NDP/sub R/). We prove that the delay of the longest path in CDP/sub R/ is lower bounded by the true delay and upper bounded by the topological delay of the circuit. Consequently, an estimate of the true delay of the resulting circuit can be computed by measuring the topological delay of the longest path in CDP/sub R/. We have developed a Functional delay ESTimation tool (FEST). Experimental results on a set of benchmarks reveal the following: approximately 50% of all paths are in NDP/sub R/ and can be ignored for true delay estimation, and the true delay estimates are on the average 15% less than the topological delay. The high level true delay estimates are accurate, as verified by comparing with the true delays obtained by gate-level timing analysis on actual implementations. Furthermore, results reveal that high level true delay estimation can be done very fast, even when gate-level true delay estimation becomes infeasible.

We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical methods to optimize transistor sizes continuously without using simulation. Consequently, it is faster than simulation-based optimizers, and more general than standard cell optimizers. We demonstrate its efficacy and accuracy on a complete dynamic adder presented, where we achieve a 54% speed-up, and final critical path delay that match Spice within 1%.

Nanomagnetic logic (NML) based digital subsystem is considered effective for low power applications, where moderate performance is acceptable. The interplay between the neighboring magnetic dots due to the magnetostatic interactions offers stable domain orientations, which is viewed as logical outputs. NML is studied at device and at primitive gate level in the past, but the functionality is not modeled at circuit level. The CMOS circuits are well studied and a quick approximation tool estimating delay and energy is highly utilized in designing large digital subsystem. A similar quick approximation modeling tool to evaluate delay of a large NML circuits is presented in this paper. The modeled approximation delay was further verified with the simulation results of NML based 1, and 2 bit full adder circuits.

As semiconductor manufacturing has entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present an NBTI gate delay model and a technique to mitigate its impact on circuit delays. First, we model NBTI impact on a gate while considering both the degradation of its own transistors and that of transistors in the adjacent gates. Simulation of our model on some ISCAS-85 benchmark circuits reveal that NBTI can cause up to 19.00% additional delay to a gate due to its own transistors degradation and up to 4.80% delay due to transistors degradation in adjacent gates after 10 years operation, resulting in a total delay of 23.80%. Therefore, we propose a transistor sizing techniques that not only mitigates NBTI induced delay of the gate under consideration but also minimizes its impact on the adjacent gates. Preliminary results of the mitigation technique applied to ISACAS-85 benchmark circuits show that with an average of 12% area overhead, the circuit delay will not exceed 15% after 10 years operation (i.e.; the introduced sizing technique realizes a delay reduction of about 45% as compared to the original circuit).

As the critical dimensions of MOSFETS are continuously shrinking, to achieve the high speed at present technology supply voltage is a challenging task for VLSI designers. At low supply voltage, maintain the high speed of integrated circuit and low-power dissipation is the major challenge for circuit designers. MTCMOS is the most useful technique for leakage power reduction in VLSI circuits. MTCMOS has some limitations in terms of delay and area due to extra SLEEP transistors. Area penalty at MTCMOS can be overcome by using a clustering technique, where a single SLEEP transistor is used for a number of integrated circuit cells. By proper sizing of sleep transistor in the cluster, it will overcome delay and area penalty in MTCMOS circuits with low leakage current. In this paper, we propose a technique for selecting proper sizing of sleep transistor for cell cluster under defined/marginal delay penalty. The proposed technique is tested on basic inverter cells circuit and from simulation results, we by properly sized SLEEP transistor achieve the high speed of operation and it is improved 2X times compared to conventional MTCMOS circuit. Here, we have also considered ground bouncing and power bouncing noise, and reduction in both is observed in the simulation result.

With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, speed binning of the high performance VLSI chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, the authors have proposed a novel on-chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-chip speed binning.