Power and area optimization by reorganizing CMOS complex gate circuits

Dynamic logic is susceptible to noise, especially in the ultra-deep submicrometer dual threshold voltage technology. When the dual threshold voltage is applied to the domino logic, noise immunity must be carefully considered since the significant subthreshold current of the low threshold voltage transistor makes the dynamic node much more susceptible to noise. In the first part of this paper, we introduce a new keeper transistor sizing method to determine the optimal keeper transistor size in terms of speed, power, and noise immunity. With the use of data obtained by presimulation, it is unnecessary to simulate all the design corners corresponding to the feasible NMOS evaluation transistor size ranges to find the optimal keeper transistor size. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all the domino logic gates. In the second part of this paper, we propose a new dual threshold voltage domino logic synthesis with the keeper transistor sizing to minimize the power consumption while meeting delay and noise constraints. With the optimal keeper transistor size determined by the proposed keeper transistor sizing method, the dual threshold voltage assignment to domino logic can be simplified to the discrete threshold voltage selection. Experimental results for ISCAS85 benchmark circuits show significant savings on leakage power and active power.

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.

With the continuing trends towards smaller, faster and more complex chips, there is an ever increasing need for new CAD tools and methodologies to support the reuse of larger building blocks, i.e., move from current cell-based methodologies and tools to higher level macro-block and mega-cell based designs. This paper presents a CAD toolset that supports both top-down design methodology (partitioning, floorplanning and synthesis), and bottom-up electrical and physical implementation (e.g. transistor sizing, block characterization, and layout generation) for block-based mixed signal ASIC designs.

Accurate modeling of CMOS logic gates for timing and power characterization is a very important task in integrated circuits technology since it facilitates significantly the design phase. Parametric models provide flexibility in determining the circuit performance in various design corners. However, the direct analysis of a complex CMOS gate aiming in an analytical and parametric model is a difficult and cumbersome task. An alternative way to model these gates is by using the equivalent inverter approach. According to this, an inverter with appropriate transistor widths is defined in order to present the same response with the complex gate it models. The challenge with this approach is to propose a simple method to predict the appropriate transistor widths of the equivalent inverter. Then, an analytical model for the CMOS inverter can be used to provide estimates for the complex gates. In this paper, a macro-modeling method is proposed for determining the transistor widths of the equivalent inverter and a technique for providing parametric expressions for these widths in terms of input transition time, output capacitive load, initial transistor width, supply voltage and temperature. A tool is developed to provide timing and power characterizations for the cells of a digital cell library, much faster than conventional numerical circuit simulators. The results prove the efficiency of the equivalent inverter approach in modeling complex gates.

In this paper, an original technology driven logic synthesis approach for look up table FPGAs and complex CMOS gates is presented. General functional decomposition, bottom-up construction and usage of the information relationships and measures are the key concepts of this approach. With this approach the technology mapping is trivial. The experimental results of the prototype tool that implements the approach are optimal for symmetric and are very promising for asymmetric functions.

The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. A key factor in timing analysis is the election of the delay model type. Pin-to-pin delay models are usually employed, but their application is limited in timing analysis when dealing with floating mode or complex gates. This paper does not introduce a delay model but a delay model type called Transistor Path Delay Model (TPDM). This new type of delay model is specially useful for timing analysis in floating mode, since it is not required to know the whole input sequence to apply it, and can manage complex CMOS gates. An algorithm to get upper bounds on the stabilization time of each gate output using TPDM is also introduced.

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Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.

This paper presents possible designs for high speed error tolerant adder using Gate Diffusion Input (GDI) technique. The 1-bit modified full adder (MFA) proposed in [1] is implemented using GDI technique (GDI-MFA). The GDI-MFA is extended to implement a 16-bit high speed error tolerant adder (GDI-HSETA). The performance of various configurations is studied based on metrics such as delay, area and power dissipation. The circuits have been simulated using pSPICE software. From the results it is observed that the proposed GDI-MFA has 52% less transistor count and consumes 33% less power compared to conventional adders. Results of simulation of GDI-HSETA and other adders in pSpice indicate that the proposed adder has 21.6% power reduction and 13% less transistor count. Also, based on the implementation of GDI-HSETA and existing 16-bit adders on FPGA Spartan 6 platform, it is observed that GDI-HSETA achieved power reduction compared to 16-bit adders using conventional design.

Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to high-performance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interior-point methods for semidefinite programming. The method is applied to two important sizing problems --- sizing of clock meshes, and sizing of buses in the presence of crosstalk.

This work addresses the problem of improving an nMOS PLA's speed and power consumption through modifications to the transistor sizes in the PLA. A simplified model of gate delay (lumped RC model) is used that allows rapid estimation of delays thus allowing interactive computation of optimal transistor sizes. Algorithms are presented for: a) minimization of delay through the PLA b) minimization of power consumption subject to a bound on maximum delay. Both these minima are computed subject to bounds on the transistor sizes. A prototype electrical optimization tool was compared to the PLA generation tools in the Berkeley CAD tools package (eqntott and tpla). The maximum delay through a PLA can often be reduced by a factor of 2, and power consumption along the critical paths can be reduced by 10 - 30% without increasing maximum delay.

Transistor size optimization is an important aspect of circuit design. Small and non-complex circuits can be designed easily using manual calculations and circuit simulations. But, as the complexity of circuits increases, manual design becomes too difficult and time consuming. Therefore, tools and techniques for automatic transistor sizing are of great importance in the area of circuit design. The goal of this paper is to implement Genetic Simulated Annealing algorithm as a tool for transistor sizing, and compare its performance with Simulated Annealing, one of the most popular optimization algorithm in use today. The algorithms have been tested on four different digital circuits and the results collated and compared in this paper.

The layout synthesis for pass-transistor cells (PTCs) is different from that for CMOS cells because of the various sizes of transistors used in a PTC and the imbalance in the number of pMOS and nMOS transistors. This makes it difficult to apply commonly used linear transistor placement to PTC layout. Moreover, the mixed placement with CMOS cells restricts the layout freedom of PTCs. Therefore a sandwiched selector structure and pass-transistor graph search are proposed for enabling a multi-row transistor layout and an efficient search algorithm for the diffusion layer sharing problem. Pass-transistor cells generated by ALPS (a_utomatic l_ayouter for p_ass-transistor cell s_ynthesis) are confirmed to have almost the same area density as that of manually designed cells.

An analysis of the state of art in asynchronous circuits reveals a lack of resources to support their design. When asynchronous cell libraries appear in the literature, they often accompany a demand from specific circuit designs, and are not proposed as general purpose resources to support semi-custom design styles. Moreover, currently proposed asynchronous libraries employ commercial technologies that cannot be distributed as open access. This work proposes and describes ASCEnD-FreePDK45, an open source standard cell library to support the design of asynchronous circuits. This first release of the library contains 30 different cells and is based on the FreePDK45 design kit, a predictive 45nm technology. Currently, the ASCEnD-FreePDK45 library supports both NCL and SDDS-NCL asynchronous design templates and is fully compatible with the NanGate FreePDK45 open cell library. ASCEnD-FreePDK45 relies on the ASCEnD-A design flow for its construction, which provides tools for transistor sizing, layout generation and electrical characterization. This article illustrates the use of the library with a semi-custom implementation of a 32-bit KoggeStone adder with cells from both the ASCEnD-FreePDK45 and the NanGate FreePDK45 libraries.