Increase in delay uncertainty by performance optimization

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.

Voltage-drop is a well-known signal integrity issue in very deep submicron technology. Voltage drop does not only induce circuit delay, but also reduces the circuit noise margins from lower supply voltages and creates reliability issues from electromigration. Voltage drop occurs due to the insufficient current supplied under design circuit state transitions. In this paper, a maximum transition current computation tool is developed. The proposed PIPD is a gate level path delay analysis tool used under insufficient current supplied conditions. This tool could help designers to quickly compute/estimate the longest path delay when voltage drop issues occur. With regard to this research issue, past works are pattern independent, which are worst-case assumptions. PIPD use a real functional test bench to activate gate transitions' peak current. The circuit peak current being accurate estimated in this research, which confirmed that dynamic behavior is pattern dependent. The proposed pattern dependent method is more realistic, and the measurement results might be lower and more accurate than earlier works. Using a PIPD could help design reasonable power rails. The simulation results prove that PIPD gate-level computation results are very close to the HSPICE transistor-level simulation results, with the average differing ratios being less than 8%, while the computation speed is increased 10X. Different to conventional EDA tools, PIPD also found that voltage drop is not certain to impact circuit delay times and calibrated by several real designed circuits.

Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven partitioning methods based on iterated net reweighting, partitioning, and timing analysis have been proposed (Ababei et al., 2002), as well as methods that apply degrees of freedom such as retiming (Cong et al., 2000), (Cong et al., 2002). In this paper, we identify and validate a simple approach to timing-driven partitioning based on the concept of "V-shaped nodes." We observe that the presence of V-shaped nodes can badly impact circuit performance, as measured by maximum hopcount across the cutline or similar path delay criteria. We extend traditional the Fiduccia-Mattheyses (FM) variant of the Kernighan-Lin (Kernighan and Lin, 1970) algorithm approaches to directly eliminate or minimize "distance-k V-shaped nodes" in the bipartitioning solution, achieving an attractive tradeoff between cutsize and path delay. Experiments show that in comparison to MLPart (Caldwell et al., 2000), our method can reduce the maximum hopcount by 39% while only slightly increasing cutsize and runtime. No previous method improves path delay in such a transparent manner. The new partitioner is incorporated into a placer (http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Placement/Capo/) and circuit delay is evaluated by a commercial static timing analyzer (http://www.ece.uci.edu/eceware/cadence/spl I.bar/docs/pearluser/). The empirical results show that the delay is significantly reduced, at the cost of very acceptable impacts on wirelength and runtime.

This paper addresses the problem of true delay estimation during high level design. The true delay is the delay of the longest sensitizable path in the resulting circuit, as opposed to the topological delay which is the delay of the longest path in the circuit. The existing delay estimation techniques either estimate the topological delay, which may be pessimistic if the longest path is unsensitizable or false, or estimate the true delay using gate-level timing analysis which may be prohibitively expensive. Resource sharing in high level synthesis can create false paths in the circuit implementation. Hence, determining the clock period using topological delay can be unduly conservative, resulting in excessive hardware to meet tight timing specifications. In this paper, we introduce an efficient technique to compute an estimate of the true delay. The proposed technique relies on partitioning the paths in the circuit and topological delay computation, and not on path sensitization. The paths in the implementation are partitioned into two sets given the high level information on scheduling and resource sharing: the complete determining path set (CDP/sub R/) and the nondetermining path set (NDP/sub R/). We prove that the delay of the longest path in CDP/sub R/ is lower bounded by the true delay and upper bounded by the topological delay of the circuit. Consequently, an estimate of the true delay of the resulting circuit can be computed by measuring the topological delay of the longest path in CDP/sub R/. We have developed a Functional delay ESTimation tool (FEST). Experimental results on a set of benchmarks reveal the following: approximately 50% of all paths are in NDP/sub R/ and can be ignored for true delay estimation, and the true delay estimates are on the average 15% less than the topological delay. The high level true delay estimates are accurate, as verified by comparing with the true delays obtained by gate-level timing analysis on actual implementations. Furthermore, results reveal that high level true delay estimation can be done very fast, even when gate-level true delay estimation becomes infeasible.

With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, speed binning of the high performance VLSI chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, the authors have proposed a novel on-chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-chip speed binning.

The most important feature of modern integrated circuit is the speed. It depends on circuit's delay. For the design of high-speed digital circuits, it is necessary to evaluate delays in the earliest stages of design, thus making it easy to modify and redesign a circuit if it's too slow. This paper gives an approach for efficient delay estimation in the describing phase of the circuit design. The method can statistically estimate the minimum and maximum delay of all possible paths and signal transitions in the circuit, considering the practical implementation of circuits, and information about the parameters' tolerances. The method uses a VHDL description and is verified on ISCAS85 benchmark circuits. Matlab was used for data processing.

The vertical structure of the atmospheric water vapor induces phase errors in interferometric synthetic aperture radar (SAR) data. This paper presents a simulation study to investigate whether spaceborne submillimeter radiometric observations, which can be realized with fairly high spatial resolution, are able to derive the vertical structure of the atmospheric wet delay. The accuracy of the retrieved zenith wet delay (ZWD) trend as a function of surface height is assessed in order to correct the associated height dependence of the interferometric phase error in a SAR interferogram. Using a simulated benchmark, we evaluate the errors associated with the use of both a linear and an exponential model of the behavior of ZWD as a function of the surface height. This paper shows a fairly accurate reconstruction of the trend parameters estimated from radiometer brightness temperature images, with respect to realistic atmospheric profiles provided by radiosounding observations (RAOBs). The trend parameters that we consider in this paper are the slope K for the linear model and scale height H for the exponential one. An overall better accuracy is found for the exponential model, which is more representative of the actual behavior of ZWD with height, resulting in a residual uncertainty in the path delay due to the atmospheric stratification of approximately 0.2-0.3 cm and nearly zero bias, as compared to RAOBs.

In this article, we derive a simple and accurate expression for the change in timing yield due to a change in the gate delay distribution. It is based on analytical bounds that we have derived for the moments of the circuit and path delay. Based on this, we propose computationally efficient algorithms for (1) discrete gate sizing and (2) simultaneous gate sizing and threshold voltage ( V T ) assignment so that the circuit meets a timing yield specification under parameter variations. The use of this analytical yield gradient within a gradient-based timing yield optimization algorithm results in a significant improvement in the runtime as compared to the numerical method, while achieving the same final yield. It also allows us to explore a larger search space in each iteration more efficiently, which is required in the case of simultaneous resizing and V T assignment. We also propose heuristics for resizing/changing the V T of multiple gates in each iteration. This makes it possible to optimize the timing yield for large circuits. Results on ITC ’99 benchmarks show that the proposed multinode resizing algorithm results in a significant improvement in the runtime with a marginal average area penalty and no cost to the final yield achieved.

Carbon nanotube field-effect transistors (CNFETs) show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance, and area (PPA). However, CNFET-specific additional features such as the number of tubes, pitch (spacing between tubes), tube position, and diameter in array of tubes play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, degrade the anticipated PPA benefits. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit’s performance, it is imperative to incorporate the impact of these parameters and variations. In this paper, we propose delay models [pitch-aware logical effort (PALE) and position-aware pitch factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. These models are developed based on industry standard logical effort framework. Furthermore, we present an optimization tool using PALE and PAPF to minimize the delay and area of CNFET circuits. We deploy several circuit-level techniques prior to optimizing the tubes (CNTs) in the logic gates to achieve globally optimum solution. For better optimization of the circuits, we also include the impact of wire parasitic in estimating the delay of the individual gates. Our optimization tool results in the maximum and average delay improvement by 27% and 17%, respectively, and $2.5\times $ reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art simulation and statistical-based methods.

A circuit's performance is usually measured by the delay of its longest path. A combinational circuit may contain cycles. We shall call these type of circuits combinational circuits. In order to find the delay of a cyclic combinational circuit we need to find the delay of the longest simple path, however traditional longest path algorithms cannot be applied to circuits containing cycles. Finding the longest simple path in a cyclic combinational circuit has been shown to be NP-hard. In this paper we propose an optimal algorithm to solve this problem. The approach we use here is first to replace cycles with matched sub-circuits and then compute the longest simple path of the expanded circuit. The matched sub-circuits are carefully constructed to preserve the path information of the original cyclic combinational circuit. Since the problem is NP-hard, the proposed algorithm has exponential time complexity in the worst case. Nevertheless, the experimental results demonstrate the feasibility of the proposed algorithm.

We introduce a new framework for describing path sensitization criteria in combinational networks. This framework is used to analyze and categorize several sensitization criteria proposed in the past. We discuss some misconceptions of existing sensitization criteria, and evaluate the effects of hazards on the delay of combinational circuits. Finally, we introduce a new sensitization criterion representing a lower bound on the delay of the longest sensitizable path.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we propose a new FPGA design algorithm, Maple-opt, in which technology mapping, placement, and global routing are executed so that the delay of each critical signal path in an input circuit is within a specified upper bound imposed on it. The basic algorithm of Maple-opt is top-down hierarchical bi-partitioning of regions. Technology mapping onto logic-blocks of FPGAs, their placement, and global routing are determined simultaneously in each hierarchical process. This simultaneity leads to less congested layout for routing. In addition to that, Maple-opt computes a lower bound of delay for each path with a constraint value and determines critical paths based on the difference between the lower bound and the constraint value dynamically in each hierarchical process. Two delay reduction processes are executed for the critical paths; one is routing delay reduction and the other is logic-block delay reduction. Routing delay reduction is realized such that, when bi-partitioning a region, each constrained path is assigned to one subregion. Logic-block delay reduction is realized such that each constrained path is mapped onto fewer logic-blocks. Experimental results for some benchmark circuits show its efficiency and effectiveness.

As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss. Considering the situations, variationaware designs for yield enhancement interest researchers. This paper investigates to exploit the statistical features in circuit delay and to cascade dependent instructions for reducing variations. From statistical static timing analysis in circuit level and performance evaluation in processor level, this paper tries to unveil how efficiently instruction cascading improves performance yield of processors. Cascading instructions increases logic depth and decreases the standard deviation of the circuit delay. That might improve performance yield of microprocessors. Unfortunately, however, it is found that variability reduction in the circuit level does not always mean yield enhancement in the microarchitecture level.

Complex and large systems such as smart grid and intelligent transportation systems consist of a large number of sensors, actuators and controllers. Hence machine–to–machine (M2M) communications between them are essential for full automatic control of the systems. The M2M communications is typical in the sense that it involves an enormous number of machine–type–communication (MTC) devices and data traffic patterns as well as QoS requirements vary widely depending on applications. LTE–Advanced of 3GPP is preparing a list of supportive functions for the M2M communications. To this end, a massive admission control scheme for the M2M communications was proposed. However, it poorly handles the call admission requests when the transmission interval of a device is relatively longer than its delay constraint, resulting in higher call blocking probability. This paper proposes a method that is free from such limitation and furthermore can reduce the computational overhead required for determining the call admission as long as the transmission interval and the delay meet certain conditions. The improvement in the call blocking probability and the proofs that the proposed method can satisfy the delay constraint were provided along with the simulation results.KeywordsM2M communicationsLTE-Advancedcall admission controldelay constraintQoS

The work addresses the design of hardware interface controllers for microprocessor-based systems. Interface design is required during the system integration phase to interconnect components which may use different interfacing protocols. It is shown that both the component interfacing protocols and the interface design can be described using an interpreted timed Petri net. Traditionally verification of the design is performed after the design has been synthesized. Such an approach usually requires several iterations, if the implementation violates some of the design constraints. A symbolic timing analysis is proposed to alleviate this problem: tight bounds on the interface path delays are computed using the available information from the protocol specifications prior to interface implementation. This is possible because our model can describe both circuit delays and environmental timing constraints. An example involving bus arbitration in the VMEbus is used to illustrate the analysis technique.