The efficient circuit delay evaluation/diagnosis methodology under voltage drop

Design and analysis of a low-swing driver scheme for long interconnects

This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e., the delay of long paths are shortened and the delay of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which are caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay.

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.

The aim of this thesis is to investigate novel recharging schemes for energy demand management (DM) of electric vehicles (EVs). While there has been a lot of work highlighting the importance of energy DM of EVs, most of the reported works do not expand on suggesting how such a DM system may be implemented. In this thesis the focus is on two aspects of DM system implementation. At the instantaneous control time scale, an alternative mechanism for frequency regulation with the aim of neutralising sudden changes in output power of electric generators is presented. At the recharge planning time scale, the aim is to avoid congestion and undesirable voltage drops in the distribution system, and a novel approach is presented that can improve voltage profiles. The problem of considering both voltage congestion and frequency regulation in a composite DM framework is also addressed. At the instantaneous control time scale, a novel distributed recharging rate controller is presented that is based on non-linear control and that yields a real time and distributed solution. This controller minimises communication overheads and allows EVs to join and leave at arbitrary times. From the perspective of recharging rate allocation, the controller achieves a Pareto efficient allocation which is also proportionally fair. The proposed controller is then applied to a system with a single, isolated, and unregulated synchronous machine and it is shown that the frequency can be used as proxy to the imbalance between produced and consumed electric power and hence communication overhead can be eliminated in such cases. A protocol is also discussed that can modify the controller and can implement the modified controller in a multi-machine system. Simulation is used to show the frequency regulation and fairness of recharging rates of EVs when the protocol and the modified controller are used. Subsequently, the integration of the recharging rate controller with the legacy protection system is also discussed. At the recharge planning time scale, the problem of congestion in the distribution system is addressed. Most of published literature on distribution system voltage issues deals with control of various network elements, for instance, on-load tap changers or banks of shunt capacitors on the distribution feeders. In this thesis, a complementary approach 7 8 is presented that can also improve voltage profile by scheduling EV load in such a manner that undesirable voltage drops are avoided or their severity is diminished. In this context, a novel approach is presented for recharging EVs in the same geographic neighbourhood that share the same secondary circuits when recharging. The approach is based on a numerical method called Smoothed Particle Hydrodynamics (SPH) that has been previously used by other researchers to solve the equations of fluid dynamics. The characteristics of the method used for the proposed approach as well as its performance in term of improvement in the reduction of voltage drops and its adaptation to elastic and non-elastic loads is highlighted via simulation. Finally, the approach is extended to also provide a frequency control reserve service.

As the critical dimensions of MOSFETS are continuously shrinking, to achieve the high speed at present technology supply voltage is a challenging task for VLSI designers. At low supply voltage, maintain the high speed of integrated circuit and low-power dissipation is the major challenge for circuit designers. MTCMOS is the most useful technique for leakage power reduction in VLSI circuits. MTCMOS has some limitations in terms of delay and area due to extra SLEEP transistors. Area penalty at MTCMOS can be overcome by using a clustering technique, where a single SLEEP transistor is used for a number of integrated circuit cells. By proper sizing of sleep transistor in the cluster, it will overcome delay and area penalty in MTCMOS circuits with low leakage current. In this paper, we propose a technique for selecting proper sizing of sleep transistor for cell cluster under defined/marginal delay penalty. The proposed technique is tested on basic inverter cells circuit and from simulation results, we by properly sized SLEEP transistor achieve the high speed of operation and it is improved 2X times compared to conventional MTCMOS circuit. Here, we have also considered ground bouncing and power bouncing noise, and reduction in both is observed in the simulation result.

The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has typically applied a worst case voltage drop at all points along a circuit path which leads to a very conservative analysis. We also show that in certain cases, the traditional analysis can be optimistic, since it ignores the possibility of voltage shifts between driver and receiver gates. In this paper, we propose a new analysis approach for computing the maximum path delay under power supply fluctuations. Our analysis is based on the use of superposition, both spatially across different circuit blocks, and temporally in time. We first present an accurate model of path delay variations under supply drops, considering both the effect of local supply reduction at individual gates and voltage shifts between driver/receiver pairs. We then formulate the path delay maximization problem as a constrained linear optimization problem, considering the effect of both IR drop and LdI/dt drops. We show how correlations between currents of different circuit blocks can be incorporated in this formulation using linear constraints. The proposed methods were implemented and tested on benchmark circuits, including an industrial power supply grid and we demonstrate a significant improvement in the worst-case path delay increase.

It was proposed in earlier work that change in voltage drop after aging be used to rate the performance of power contacts. In that paper it was shown that end-of-life failure criteria could be empirically modeled as a function of current for a given set of accelerated tests. This was established using a statistical model for the end-of-life change in voltage drop. The present paper expands on the previous work by extending the database to include samples with and without aging. In addition, the aged samples are exposed to accelerated-tests that go beyond the previous work. Consequently, in addition to modeling the end-of-life Criterion, the progression of degradation is modeled to complete the picture. With both the failure criteria and voltage change modeled as functions of current and thermal aging respectively, a statistical method of rating power contacts in terms of current level and expected field life is developed. The database is obtained empirically by conducting high current cycling tests after accelerated aging of tin plated power contacts. This approach enabled the development of change in voltage drop failure criteria and mean change in voltage drop as functions of current level and accelerated aging respectively. The results are analyzed using basic contact theory in conjunction with an exponential statistical model. Moreover, it is shown that current density and the associated localized power dissipation are basic physical parameters that link aging to failure criteria.

The current–voltage characteristic of magnetospheric magnetic flux tubes is studied under rather general conditions, assuming the current to be carried by collision‐free particles experiencing inertia, electric forces, and magnetic mirror forces. The approach is that of the powerful kinetic “orbital motion” theory of current collectors in plasma as developed by H. M. Mott‐Smith and I. Langmuir in 1926. When C. Davisson's 1925 condition on particle access is fulfilled, the total voltage drop is uniquely determined from the current by kinetic/geometric considerations only, without considerations of the actual space charge and electrostatic potential distribution. For any velocity distribution that is isotropic within the source cone, the current–voltage characteristic is linear for sufficiently small currents. The nature of the corresponding global flux tube electric resistance is discussed. The current–voltage characteristic is given for a variety of distribution functions (where the Maxwellian case corresponds to that studied by S. Knight in 1973) including distributions with a reduced (nonisotropic) flux in the source cone. The current–voltage characteristic is also discussed for cases where the Davisson condition is not fulfilled, when the solution method provides a lower bound on the voltage for a given current. Making assumptions on the altitude extent of the voltage drop, we can also define an upper bound on the voltage for a particular current. The magnetospheric source of particles should be taken to be located at the top of the acceleration region in order to fulfill the Davisson condition. This may limit the effective magnetic mirror ratio, such that the applicability of the linear approximation to the current–voltage characteristic is more restricted, and the saturation current is moderately small, which may lead to overvoltages, a redistribution of the current, or an increased extent of the acceleration region. Joining solutions that piecewise fulfill the Davisson condition, we can derive the current flow for a rather wide range of prescribed potential distributions. Earlier works on the Knight mechanism and related theories for determining the voltage drop along a flux tube are discussed. Determination of the electrostatic potential distribution, and verification of the Davisson condition, requires considerations of the space charge (Poisson equation), to be discussed in a second paper.

Presented are new algorithms for synthesizing Boolean functions as regular logic structures. These regular structures can be mapped directly (without place&route) to a standard-cell library designed for regularity or to locally-connected programmable devices. The advantage of regular structures is that for a planar embedding the number of nodes in the expansion level grows at most linearly with the number of expansion variables. Regularity offers a predictable solution to hard problems arising in layout, at no extra cost or at the cost of increasing the number of gates, but without necessarily increasing circuit area. Increasing the number of logic levels does not translate into an increase in overall circuit delay, because regular, neighbor-to-neighbor connections reduce the wire delay, the dominant factor in deep sub-micron technology. This paper proposes new techniques which lead to less variable repetition and significantly improve the performance of synthesis algorithms. Experimental results much better than previously published data are very encouraging.

Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven partitioning methods based on iterated net reweighting, partitioning, and timing analysis have been proposed (Ababei et al., 2002), as well as methods that apply degrees of freedom such as retiming (Cong et al., 2000), (Cong et al., 2002). In this paper, we identify and validate a simple approach to timing-driven partitioning based on the concept of "V-shaped nodes." We observe that the presence of V-shaped nodes can badly impact circuit performance, as measured by maximum hopcount across the cutline or similar path delay criteria. We extend traditional the Fiduccia-Mattheyses (FM) variant of the Kernighan-Lin (Kernighan and Lin, 1970) algorithm approaches to directly eliminate or minimize "distance-k V-shaped nodes" in the bipartitioning solution, achieving an attractive tradeoff between cutsize and path delay. Experiments show that in comparison to MLPart (Caldwell et al., 2000), our method can reduce the maximum hopcount by 39% while only slightly increasing cutsize and runtime. No previous method improves path delay in such a transparent manner. The new partitioner is incorporated into a placer (http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Placement/Capo/) and circuit delay is evaluated by a commercial static timing analyzer (http://www.ece.uci.edu/eceware/cadence/spl I.bar/docs/pearluser/). The empirical results show that the delay is significantly reduced, at the cost of very acceptable impacts on wirelength and runtime.

With high operating frequencies and scaled geometries, the power and ground distribution network requires greater design optimization to effectively provide higher current flow with minimal voltage variations. Low supply voltages and high currents in ICs place stringent constraints on the P/G distribution networks. Higher frequencies and smaller transistors produce shorter transition times, such that \(L\left (di/dt\right )\) voltage drops can exceed IR voltage drops. All of these factors require the inductance to be considered in the design of on-chip P/G distribution networks. To optimize these large scale P/G distribution networks, the inductance needs to be accurately and efficiently determined.

Based on simulated beam loss scenarios at LHC, fully depleted CMS silicon strip detectors and sensors were exposed to 42 ns long beam spills with 10 protons per spill at PS at CERN. This high ionising dose is sufficient to shortcircuit the silicon sensors. The dynamic behaviour of bias voltage, leakage currents and voltage drop over coupling capacitors had been monitored during the impact. The results of preand postqualification as well as the dynamic behaviour will be presented.

This paper addresses the problem of true delay estimation during high level design. The true delay is the delay of the longest sensitizable path in the resulting circuit, as opposed to the topological delay which is the delay of the longest path in the circuit. The existing delay estimation techniques either estimate the topological delay, which may be pessimistic if the longest path is unsensitizable or false, or estimate the true delay using gate-level timing analysis which may be prohibitively expensive. Resource sharing in high level synthesis can create false paths in the circuit implementation. Hence, determining the clock period using topological delay can be unduly conservative, resulting in excessive hardware to meet tight timing specifications. In this paper, we introduce an efficient technique to compute an estimate of the true delay. The proposed technique relies on partitioning the paths in the circuit and topological delay computation, and not on path sensitization. The paths in the implementation are partitioned into two sets given the high level information on scheduling and resource sharing: the complete determining path set (CDP/sub R/) and the nondetermining path set (NDP/sub R/). We prove that the delay of the longest path in CDP/sub R/ is lower bounded by the true delay and upper bounded by the topological delay of the circuit. Consequently, an estimate of the true delay of the resulting circuit can be computed by measuring the topological delay of the longest path in CDP/sub R/. We have developed a Functional delay ESTimation tool (FEST). Experimental results on a set of benchmarks reveal the following: approximately 50% of all paths are in NDP/sub R/ and can be ignored for true delay estimation, and the true delay estimates are on the average 15% less than the topological delay. The high level true delay estimates are accurate, as verified by comparing with the true delays obtained by gate-level timing analysis on actual implementations. Furthermore, results reveal that high level true delay estimation can be done very fast, even when gate-level true delay estimation becomes infeasible.

Detecting hardware Trojan is a difficult task in general. The context is that of a fabless design house that sells IP blocks as GDSII hard macros, and wants to check that final products have not been infected by Trojan during the foundry stage. In this paper we analyzed hardware Trojan horses insertion and detection in Scalable Encryption Algorithm (SEA) crypto. We inserted Trojan at different levels in the ASIC design flow of SEA crypto and most importantly we focused on Gate level and layout level Trojan insertions. We choose path delays in order to detect Trojan at both levels in design phase. Because the path delays detection technique is cost effective and efficient method to detect Trojan. The comparison of path delays makes small Trojan circuits significant from a delay point of view. We used typical, fast and slow 90nm libraries in order to estimate the efficiency of path delay technique in different operating conditions. The experiment's results show that the detection rate on payload Trojan is 100%.

To modernize it's rolling stock and increase quality of the municipal public transport service, city of Zagreb, through its public transport company (ZET) made an investment into 140 new NT2200 trains. These trains incorporate asynchronous motors and AC/DC converters, as the tram electrical system is supplied by 660 V DC power. Coincidentally, the occurance of outages in the network increased 60%. This problem doesn't just present financial losses for the public transport company, but also decreases quality of service. In a project study, conducted by the Faculty of electrical engineering and computing, the entire physical and electrical network was modeled and dynamically simulated to discover voltage drops, power losses and peak currents, which have so far been unknown on a system-level. It has been determined that the existing power supply facilities are sufficient to fulfill demands of the existing transportations trains, however with multiple changes to the distribution cables and section separators to enable continuous system operation. Using an optimization procedure, new connecting places for supply lines and cables were determined. The results were also checked by a steady-state model. With projected reinforcements, voltage drops and currents are reduced, and thus the protection devices can be set to lower breaking currents. As a result of electrical network performance indicators improvements, the company will save over 6 million EUR annually.