Delay fault coverage and performance tradeoffs

Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded the scan wire-length overhead. In this paper we consider both dummy flip-flop and wirelength costs, and focus on post-layout formulations that capture the achievable tradeoffs between these costs and delay fault coverage in scan chain synthesis.

With the increased densities of integrated circuits, several different types of faults can occur. Faults in digital circuits resulting from random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work in statistical modeling and analysis for delay fault testing generally assumes that at most a single delay fault can occur along any given path in the circuit under test. In this paper we investigate the statistical effect of multiple delay faults along any path in a circuit under test, and predict the path delay fault probabilities as well as the maximum number of path delay faults for both combinational and sequential benchmark circuits. We begin with the development of a statistical model for path delay faults in VLSI circuits [4], which takes into account multiple delay faults along any signal path.

An approach to the design of multilevel, multi-output combinational logic circuits in which all path delay faults are detectable by robust tests is proposed. Inadequacies of previous approaches for synthesis for testability of path delay faults are discussed. A necessary and sufficient condition for the existence of a hazard-free robust test for a path is stated. Violation of this condition is adopted as the criterion for identifying the paths, in a given circuit, which are not testable by hazard-free robust tests. Transformation methods to render these paths testable are proposed. >

The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first category of circuits, but not for synchronous sequential circuits. So, this paper concerns delay fault diagnosis for non-scan circuits. A preliminary version of the proposed method is first given. New concepts for allowing path tracing in the proposed diagnosis process (identification of self-masking) are also presented. As the method is based on path tracing through the sequential circuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine. Results of experiments on ISCAS-89 benchmark circuits are finally discussed.

In this work we propose a novel concept called state tuple to represent the states of lines in a circuit for the generation of two pattern tests. The proposed approach is described in detail for generating robust two pattern tests for path delay faults in standard scan designs. Using the proposed approach we also report experimental results of a test generator for robust path delay faults in standard scan designs. The results show that the test generator achieves high efficiency with reduced implementation complexity.

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first propose a new technique to identify and test primitive faults. A primitive fault is a path delay fault that has to be tested to guarantee the performance of the circuit. Primitive faults can consist of single- (SPDF's) or multiple path delay faults (MPDF's). Testing strategies for single primitive faults exist. In this paper, we focus on identifying and testing multiple primitive faults. Identification and testing of these faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the SPDF model, and (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The SPDF's contained in a multiple primitive fault have to merge at some gate(s). Our methodology can quickly (1) rule out a large number of gates as possible merging gates for primitive faults, and (2) prune the combinations of paths that can never belong to any primitive fault. Our identification procedure also finds a test for the fault. We present a complete algorithm for identifying and testing double path delay faults, Identifying and testing all primitive faults is impractical for large designs. This is because no efficient methods are known for testing primitive faults that include a large number of paths. However, to guarantee that the performance of a digital circuit is not affected by timing defects, it is necessary to test all primitive faults. Our second contribution is a new design for testability method. Our method guarantees that only primitive faults with at most two paths can exist in the circuit in the test mode. The main idea is to efficiently identify a small set of signals for inserting test points to eliminate primitive faults with more than two paths. Our test points only provide controllability. Addition of a single test point can lower the cardinality of several primitive faults. Our approach efficiently re-evaluates primitive delay fault testability of the circuit after insertion of a test point. After a few iterations only primitive faults with at most two paths can exist in the circuit in the test mode. Experimental results on several multilevel combinational benchmark circuits are included to demonstrate the usefulness of our techniques.

Path delay fault model is the most suitable model for detecting distributed manufacturing defects which can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs is very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths in the circuit. Our results show that it is possible to obtain circuits with a significant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points into the circuit can help reducing the number of such paths in the given design.

We present a novel and efficient method to identify all primitive single and multi path delay faults (PDFs) in multi-level combinational circuits. Our method is the first one to successfully target the primitive PDF identification problem for multi-level circuits-previous research results in this area have been limited either to the identification of primitive PDFs only for 2-level circuits, or to the identification of only a subset of the complete set of paths which need not be tested for delay faults. Our primitive PDF identification procedure is based on determining which paths or sets of paths determine the signal stabilization time at the circuit outputs. We demonstrate the feasibility of the approach for mid-sized benchmark circuits.

We present a novel framework to identify all the robustly testable and untestable path delay faults in a circuit. The method uses a combination of decision diagrams for manipulating path delay faults and Boolean functions. The approach benefits from processing partial paths or fanout free segments in the circuit rather than the entire path. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology identifies 350% more testable faults in the ISCAS'85 benchmark C6288 than any existing technique by utilizing only a fraction of the time compared to earlier work.

A new simulation-based method uses single-input change (SIC) vectors to derive tests efficiently for singly testable (ST) path-delay faults (PDFs). A PDF is ST if there exists a delay test that guarantees its detection when it is the only PDF in the circuit. It is known that an ST PDF must have a single-input change test. We utilize this result and present a fault simulator that is specifically tuned to simulate single-input change vectors efficiently. We assign random values to all inputs, and then propagate rising and falling transitions from each input while all other inputs are held steady. We present a 16-valued algebra with which rising and falling PDF's from all inputs are concurrently simulated. Using a suitable encoding for signal values, gates are evaluated directly through Boolean operations, and all computation stages use machine word parallelism. Results on the ISCAS'85 and '89 benchmarks show that the approach is superior to another published method in terms of both fault coverage and execution time.

In this paper, we propose a new testability metric for path delay faults. The metric is computed efficiently using a non-enumerative algorithm. It has been validated through extensive experiments and the results indicate a strong correlation between the proposed metric and the path delay fault testability of the circuit. We further apply this metric to derive a path delay fault test application scheme for scan-based BIST. The selection of the test scheme Is guided by the proposed metric. The experimental results illustrate that the derived test application scheme can achieve a higher path delay fault coverage in scan-based BIST. Because of the effectiveness and efficient computation of this metric, it can be used to derive other design-for-testability techniques for path delay faults.

An efficient delay test generation (DTEST GEN) system for combinational logic circuits is presented. In the DTEST GEN system, delay testing problems are divided into gross delay faults and small delay faults separately so that the tradeoff between the levels of delay testing effort and the confidence levels of proper system operation can be explored. Complete automatic test pattern generation (ATPG) algorithms are proposed for both gross delay faults and small delay faults. A novel timing analysis method for delay test generation which uses a conventional depth-first search technique and a novel functionality analysis technique is introduced. The functionality analysis technique examines, necessary conditions for a given delay fault to be testable and estimates the upper bound of the good circuit propagation delay of the longest sensitizable path passing through the fault site. Several benchmark results are demonstrated for both gross delay fault testing and small delay fault testing. >

Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test issues. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage. The main goal of this paper is to investigate a methodology to improve the delay fault coverage of a given test set of functional test programs. We propose to exploit existing Design-for-Test architecture to apply in a smarter way the functional programs. Then, we combine those programs with the classical at-speed LOC and LOS delay fault testing schemes to further increase the delay fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage.

Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs