Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study

High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption in functional mode of microprocessor cores. The obtained power consumption will be used as threshold to tune the power consumed during testing. This paper investigates the impact of re-using such functional test programs for testing purposes. We propose to apply them by exploiting existing DfT architecture to maximize the delay fault coverage. Then, we combine them with the classical at-speed LOC and LOS delay fault testing schemes to further increase the fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage while respecting the functional power budget.

Diagrammatic programming environments provide a unique challenge for the developers of test software. These cost effective environments facilitate access to technologies such as VXI, provide speedy development of highly effective user interfaces, and eliminate many of the tasks often associated with hardware integration in complex test systems. Nonetheless, difficulties can arise when designing functional and diagnostic test software in this environment. This paper introduces VISTA, a promising new architecture which allows users to elude most of the difficulties of building detailed functional and diagnostic Test Program Sets (TPSs), while taking full advantage of the benefits of diagrammatic programming environments. Here we examine an implementation of the VISTA architecture, the integration of advanced diagnostics, and the use of diagrammatic programming as a test language cross compiler.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testing for delay faults in heavily gated clock designs has the major test challenges of reduced fault coverage and high test power consumption. In the scan-test method, gated clocks are often simplified and replaced with global test clocks. As such, partial clocking by the gated clocks is not inherited in test operations. Global clocking suffers from delay fault coverage loss because a sensitization state cannot easily be created due to the increased state dependence in functional paths, as compared to partial clocking. The global clocking scheme in the test mode is not adequate for low-power designs either, because the power consumed during a test operation exceeds that used during a normal operation. The power grid may not be sufficient to support the power drawn during testing, perhaps resulting in overkilled devices. It is therefore critical that power consumption be maintained under a safe limit, even during testing. In the proposed method, partial clocking in gated designs is preserved to the maximum possible to create more reachable states, thereby increasing transition fault coverage and reducing test power during launch and capture cycles. A transition fault simulator was developed, and it demonstrated higher transition fault coverage and reduced test power for ISCAS-89 circuits when partial clocking is used.

Article Free Access Share on Delay fault coverage and performance tradeoffs Authors: William K. Lam View Profile , Alexander Saldanha View Profile , Robert K. Brayton View Profile , Alberto L. Sangiovanni-Vincentelli View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993Pages 446–452https://doi.org/10.1145/157485.164970Published:01 July 1993Publication History 89citation253DownloadsMetricsTotal Citations89Total Downloads253Last 12 Months17Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Existing methodologies for determining gate delay fault coverages are shown to have certain deficiencies. A new and more realistic delay model is presented with the ultimate goal of ensuring error-free circuit operation through obtaining true fault coverages that extend upto the actual slacks. Methods are given that achieve such coverages when possible. Results of experiments performed to evaluate the practical benefits of the proposed methods over previous approaches are given. The proposed method over previous approaches are given. The proposed method based on varying the sampling time of the circuit outputs during testing is seen to produce very high delay fault coverages upto the actual circuit slacks, as opposed to methods based on fixed output sampling times.

Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded the scan wire-length overhead. In this paper we consider both dummy flip-flop and wirelength costs, and focus on post-layout formulations that capture the achievable tradeoffs between these costs and delay fault coverage in scan chain synthesis.

The paper is dealing with the in-field test of the decode unit of RIS C processors through functional test programs following the SBST approach. The paper details a strategy based on instruction classification and manipulation, and signatures collection. The method does not require the knowledge of detailed implementation information (e.g., the netlist), but is based on the Instruction Set of the processor. The proposed method is evaluated on an industrial SoC device, which includes a PowerPC derived processor. Results demonstrate the efficiency and effectiveness of the strategy; the proposed solution reaches over 90% of stuck-at fault coverage while an instruction coverage based approach does not overcome 70%.

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

We present a technique that generates high-quality functional in-field self-tests specifically targeting deep learning (DL) accelerators. These functional tests can be applied in the field during normal operation of a DL accelerator, which is crucial to ensure that the safety and/or reliability requirements are met for any given application, including safety-critical applications such as self-driving cars, robotics, and more.Our technique takes advantage of special architectural characteristics and application properties to achieve high functional test coverage while incurring minimal system-level costs. Moreover, we devise different strategies for the compute units (which support computation operations) and the control units (which control data movement) because these two types of units exhibit different properties. For the compute units of a DL accelerator, we first use combinational ATPG to generate test patterns with high test coverage, which is possible because these units do not contain complex sequential logic. Next, we map the ATPG patterns to one or more equivalent deep neural networks (DNNs) that can be directly executed on the accelerator, which is possible given the well-defined dataflow/reuse algorithm of a DL accelerator. For the control units, we leverage the property that typically only one or a few fixed DNNs are deployed at a time in many application domains (e.g., self-driving cars). Thus, it is sufficient to target only the faults that can directly affect the correctness of the DNNs that are currently deployed. This is done by executing different layers of each target DNN using carefully-crafted input and weight values to maximize test coverage while minimizing test time.We apply our technique using Nvidia’s open-source accelerator as a case study to demonstrate its efficacy. Our results show that our technique achieves high test coverage. For the compute units, 99.9% single stuck-at functional test coverage is achieved. For the control units, we are able to prove that, given any target DNN, 100% coverage can be achieved for a large class of single and multiple fault models. The in-field functional self-test time is also very low, < 17 ms for various representative DNNs. These functional tests can be applied during boot-up, reset, and even concurrently with normal operation by executing DNN test programs directly on the accelerator, without requiring any test support in the hardware.

Hewlett-Packard's marketing research over the past several years reveals that the chief concern of computer-aided test (CAT) managers is to reduce the cost and effort of program development. CAT software tools and techniques for rapidly developing high-performance test programs at lower costs and with less effort are discussed. Functional test manager (FTM) and interactive test generator (ITG) software packages work together to provide a very easy functional test software solution. FTM provides a wide range of capability designed to help automate functional test applications. ITG is a very easy-to-use tool for generating instrument control and measurement procedure software. It makes it possible to generate the instrument control portion of functional test programs without having to search through manuals looking for instrument control mnemonics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length. >

Delay testing continues to gain importance as manufacturers try to meet stricter requirements for higher performance and higher density integrated circuits. The methodology to obtain a set of high quality gate delay fault detecting tests is unfortunately computationally intensive enough to be intractable for reasonably large VLSI circuits; parallelization of these computations is thus an attractive scenario. We present, for the first time, distributed algorithms for gate delay fault simulation and fault coverage determination through test quality evaluation. These algorithms are implemented over a network of workstations, which is normally available at most design labs, and thus do not rely os the use of very specialized, expensive, or difficult-to-access hardware. These algorithms are theoretically analyzed, and experimental studies of their implementation are reported. The results conform to the theoretically predicted performance, with speedups of up to 10 being obtained with 15 workstations. >

FPGA Controlled Interface Boards (FCIB) are widely used in electronic systems in order to meet the control, communication and I/O requirements. These boards employ FPGAs to control multiple signal input/output blocks, communication interfaces (RS232/422, CAN, ETH, PCIe etc.), ADC/DAC circuits, and other general purpose circuits. Production tests of FCIBs are vital since a single fault in the Unit Under Test (UUT) may cause serious consequences (engineering, rework, time, money costs) at higher levels of integration. Test requirements of UUT are specified as the first step of the test design process to define the test coverage. As the second step, test is designed at high level by specifying the building blocks of the test program set (TPS). In this step, hardware and software components are designed and implemented. Finally, TPS is verified after integrating all components. These three steps can be concluded briefly as Test Program Set requirements, design and implementation, verification. In addition to these test development steps, test design process should be carried based on the general automated test development considerations. These principles can be grouped in five subjects. Firstly, all the test steps in the testing procedure should be repeatable. Secondly, since these tests will be used in mass production, the test duration should be as short as possible while verifying all interfaces precisely and reliably. Thirdly, tests should require minimum amount of operator interaction. It should be fully automated-if possible- to reduce the test duration and errors due to operator interaction. Fourthly, test steps should not only catch the errors but also localize them to a circuit block on the board. This helps to repair the faulty parts quickly in production. Finally, all tests should be done with minimum amount of test equipment. After defining the UUT specifications and TPS requirements, there are two methods that could be applied in the test design process of the FCIB. The first one is to control all interfaces with embedded test code running on FPGA of UUT and using interface specific test devices to verify the circuit block. In order to test the interfaces of the FCIB, the test devices should be able to manage the signals in two directions, from FCIB and to FCIB. The test flow is controlled from external world through a UUT interface-generally UART. To make the test faster and minimize the operator interaction, a high-level test software is designed in LabVIEW or a similar environment to automatize the test procedure. The second method is using another verified FCIB, namely a Golden Board, which helps to communicate through all interfaces of the UUT and verify it functionally. In this method, test designer should define the hardware interface between the boards, and construct a test procedure accordingly. Next, embedded code for the FPGAs on the Golden Board and UUT should be developed in order to simulate the functionality of the UUT. The synchronization and handshaking of two FPGA codes also becomes important to manage test flow. A high-level test software may also be developed in LabVIEW or a similar environment depending on the test design. Both of two methods have their own advantages and disadvantages. In this paper, the two methods of designing an automated test for FPGA Controlled Interface Boards will be discussed. They will be compared according to their workload of development, capability of locating errors, test duration and efficiency of the testing (coverage, probability of error occurrence).

We investigated the influence of the random generation methods to the results of the functional delay test generation. There are the three possibilities: random generation of values 0 and 1 when the probability for the appearance of each value is 50% in every bit of test pattern; random generation of large integer values, which then are split into the sequences of 0’s and 1‘s according to the rules of the conversion of the decimal number to the binary number; anti-random generation when the presence of the earlier generated patterns is taken into account. We adopted the anti-random generation for the functional delay faults. The obtained results of the investigation indicate that the random generation has the direct influence to the results of the functional delay test generation. The largest coverage of transition fault is obtained when the anti-random generation is employed.