Delay testing considering crosstalk-induced effects

In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC floorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a floorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC floorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.

Single Ended Loop Testing (SELT) is generally the most preferred and economical way for estimating loop topology. In this paper we implement a combination of Correlation Time Domain Reflectometry (CTDR) and Frequency Domain Reflectometry (FDR) for loop topology estimation. SELT loop estimation is performed in two phases, a measurement phase and an interpretation phase. The major advantage of the proposed method is that the measurement is done by reusing most of firmware modules in a typical DSL broadband modem without affecting the other services in the bundle. As the measurement is done online the effect of cross talk noise and AWGN noise is also considered. No prior knowledge of the network topology is required. While CTDR is used for an initial estimate, FDR proceeds further to obtain more exact estimates. Simulations performed on a typical ANSI loops using this method shows good prediction capability.

Coupling Of Synthesis And Layout: Challenges And Solutions

Due to scaling induced effects, CMOS circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. Researchers mostly considered SE transients as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications such as avionics, military and medical applications, additional sources such as SE induced soft delays, clock jitters, false clock pulses and crosstalk effects need to be included in soft-error reliability analysis. As technologies advance, coupling effects among interconnects increasingly cause SE transients to contaminate electronically unrelated circuit paths, which can in turn increase the "SE susceptibility" of CMOS circuits. This work focuses on such coupling induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SE transient effects, and crosstalk contribution to soft error rate has been examined. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. Results show that, in newer technologies, the SE coupling delay becomes quite comparable to soft delay effect, although caused indirectly by cross-coupling effects. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.

Integrating analog and radio-frequency (RF) circuits with digital blocks on a C M O S system-on-a-chip (SoC) has drawn a lot of attention, recently. One major obstacle at this high level of integration is the substrate noise, which results in undesired interaction between these circuits through the common substrate. Analog circuits are the main victims of such interactions; consequently, understanding the behaviour of substrate noise and performance degradations it causes, is indispensable for analog designers. This work addresses three aspects of substrate noise. First, substrate noise is characterized in the time and frequency domains to identify major parameters that control substrate noise generation, propagation, and reception. Effects of many parameters on the amount of noise generation and coupling are also studied. Second, this thesis investigates the noise impact on analog circuits from a circuit-level point of view by introducing a new small-signal model of the M O S device, which accounts for the substrate noise effects. While most works have focused on system-level or signallevel analysis, study of the noise from a circuit-level point of view is more beneficial for analog designers because it gives them more insight on how to improve the substrate noise rejection capability of their designs. Finally, noise reduction techniques are revisited in this work. The use of passive guardrings is reviewed in detail and the effects of many design parameters on the amount of noise attenuation provided by these structures are studied. The behaviour of guard-rings in different substrates are also discussed.

Reducing the effect of crosstalk noise from defocused multi-depth holographic image with a rasterize encoding method

Much attention has been paid toward signal and power integrity in devices, circuit boards and entire systems. Resonances set up between the power and ground planes due to multiple reflections from the edges of the circuit board will affect signal integrity. The impedance seen by a via passing between the power and ground planes can be very high at the resonant frequencies. This gives rise to the effects of crosstalk and simultaneous switching noise (SSN) which would adversely effect the operation of the device. An attempt has been made in this paper to cover all the topics in earlier papers (Shi et al., Proc. Electron. Comp. Technol. Conf., 2001, and Adsure et al., Proc. IPAC'01 Conf., 2001), which describe a method to incorporate (absorbing) at the edges of a circuit board to reduce the wave reflections. The lossy material is usually a of very high resistivity but which shows large magnetic losses at UHF and microwave frequencies. Thus this is suitable to be placed directly between the power and ground planes without introducing any DC leakage currents. Experiments were carried out on a bare copper circuit board with FR-4 dielectric. The absorber used in the experiments is available commercially in flexible, castable and hard dense forms. It is shown that it is possible to reduce the impedances at the resonant frequencies to quite an extent over a broad frequency band by applying the at the edges of the board. Various configurations of applying the are also described.

Deep-Sub-Micron (DSM) technologies of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, it's important to consider improving crosstalk noise at initial phase of layout design. In this paper, we proposed a novel crosstalk-driven placement algorithm. The proposed algorithm based on genetic algorithm (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving crosstalk noise, reducing power consumption, improving interconnection delay and dispersing wire congestion. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of power, delay and congestion. Results show improvement of 6.7% for crosstalk noise on average.

As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a greater role in sub-100 nm technologies and creates signal integrity issues. It is vital to consider supply voltage noise effects: 1) during design validation to apply sufficient guardbands to critical paths, and 2) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure is proposed to maximize PSN effects on critical paths considering the impact of local voltage drop. The proposed pattern generation and validation flow is implemented on the ITC'99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed on the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practised in industry.

Substrate noise is a major concern for the realization of radios on a mixed-signal chip. This paper presents a method for substrate noise immune VCO design. A sensitivity analysis is proposed to investigate and reduce the impact of substrate noise on a 900 MHz LC-tank VCO. The proposed method provides a designer with the necessary insight to control the performance degradation by substrate noise. Impact via the on-chip current reference is explained and solved reducing the overall impact with 10 dB. The VCO on-chip ground is recognized as a major entry point for substrate noise. Guarding is used to attenuate coupling of substrate noise into the VCO ground up to - 90 dB in this 0.18 /spl mu/m design on a lightly doped substrate. In this way a high immunity for substrate noise is achieved.

High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.

Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL convention logic (NCL) and traditional clocked Boolean logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 μm process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta-sigma modulator (DSM) example. The signal-to-noise ratio performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency.

Simultaneous switching events in the clock lines and almost simultaneous switching events of sequential and combinational logic elements cause large L/spl middot/di/dt and IR voltage variations in the power and ground network of a circuit. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose a genetic algorithm based clock scheduling approach for minimizing the number of simultaneous switching events such that the power supply noise is suppressed. We ensure that in any generation of the genetic algorithm process, there will be feasible clock schedules present in the gene pool by the use of gene therapy. Experimental results on benchmark circuits show an average reduction of 26.2% in the peak current, an average reduction of 37.9% in the current swing, and an average reduction of 46.2% in voltage variations in the power lines.

Modern network-on-chip (NoC) systems face reliability issues due to process and environmental variations. The power supply noise (PSN) in the power delivery network of a NoC plays a key role in determining reliability. PSN leads to voltage droop, which can cause timing errors in the NoC. This paper makes a novel contribution towards formally analyzing PSN in NoC systems. We present a probabilistic model checking approach to analyze key features of PSN at the behavioral level in a \(2\times 2\) mesh NoC with a uniform random traffic load. To tackle state explosion, we apply incremental abstraction techniques, including a novel probabilistic choice abstraction, based on observations of NoC behavior. The Modest Toolset is used for probabilistic modeling and verification. Results are obtained for several flit injection patterns to reveal their impacts on PSN. Our analysis finds an optimal flit pattern generation with zero probability of PSN events and suggests spreading flits rather than releasing them in consecutive cycles in order to minimize PSN.

Noise effects such as power supply and crosstalk can significantly affect the performance of deep submicron designs. These delay effects are highly input pattern dependent. Existing path selection and timing analysis techniques cannot capture the effects of noise on cell/interconnect delays. Therefore, the selected critical paths may not be the longest paths and predicted circuit performance might not reflect the worst-case circuit delay. In this paper, we propose a path selection technique that can consider power supply noise effects on the propagation delays. Next, for the selected critical paths, we propose a pattern generation technique for dynamic timing analysis such that the patterns produce the worst-case power supply noise effects on the delays of these paths. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered vs. when these effects are ignored. Thus, they validate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.