Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs

A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.

In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.

A digital background calibration technique to compensate for the finite opamps dc gain in pipelined analog-to-digital converters is presented. By transforming the ADC and measuring the gain ratios between different configurations, a background calibration is possible without interrupting the ADC operation or injecting a calibration signal. A modified multiplying digital-to-analog converter (MDAC) is proposed. This new MDAC allows the ADC to toggle between different configurations to create a reference signal used for the calibration. Simulations results prove the effectiveness of this new method.

This paper presents a digital background timing-skew calibration technique with high accuracy and bandwidth in time-interleaved (TI) analog-to-digital converters (ADCs). Compared with other calibration works, it features three highlights. Firstly, the proposed DCSD-based step-by-step and grouping calibration scheme can effectively improve the correction accuracy by minimizing the root mean square (RMS) value of the detected timing skews. Secondly, the linear compensation for a 13-taps FIR filter and the decimation-calibration-interpolation working pattern are used to expand the calibration effective bandwidth to the whole first Nyquist zone from different perspectives. Thirdly, the binary search is employed, instead of LMS algorithm, in order to meet the compensation requirement for FIR filter and improve the convergence speed and accuracy significantly in timing-skew detection. As a result, the proposed technique achieves the widest calibration bandwidth and higher accuracy compared to other fully digital calibration techniques while having the great convergence speed. Simulation model in MATLAB and FPGA-based hardware verification are employed to demonstrate its significant improvement on the performance and hardware overhead of the TI-ADCs. Finally, the proposed technique is employed in a 10-bit 2.5 GS/s 4-way TI-SAR ADC fabricated by standard CMOS 28nm process. The measurement results show that with the proposed technique, the SFDR and SNDR are improved by 18.9 and 17.9 dB at Nyquist frequency, respectively.

The paper deals with a novel 12-bit low power switched-capacitor (SC) pipelined analog-to-digital converter (ADC). The problems caused by using of SC technique are compensated or roughly attenuated by means of combination of well-known analog-domain techniques and new digital background calibration technique. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches the fully differential circuitry was utilized. The special op-amps and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the op-amps was taken into account too. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.

A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional- N phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma (ΔΣ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL's phase noise from DMRO flicker noise, which would otherwise degrade the PLL's in-band phase noise, and from ΔΣ FDC quantization error, which would otherwise degrade the PLL's phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed ΔΣ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a total jitter that ranges from 151 to 270 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> as a result of fractional spurs, and a worst-case fractional spur of -49 dBc without requiring nonlinearity calibration.

The problem of slow convergence speed exists in the correlation-based digital background calibration techniques for the pipeline ADC. The proposed improved techniques reduce the signal-dependent interference amplitude by clipping MSBs off the ADC output. Meanwhile, the exponential averager is introduced into the LMS iteration. These means can not only calibrate capacitors mismatch in MDACs and the finite gain and bandwidth of the interstage opamp, but also converge more than 20 times faster than normal correlation-based calibration techniques. A behavioral model of 12bits pipeline ADC with 2% interstage gain error in the first stage is presented to verify the efficiency of the calibration techniques. With calibration, simulation results show that SFDR enhances from 69dB to 98dB and SNDR enhances from 53.8dB to 73.5dB.

Many digital background calibration techniques exist which correct for offset, gain, timing and bandwidth mismatches in time-interleaved (TI) ADCs. Some require an additional reference channel, whereas others are blind and rely on the presence of a band where no signal is present (usually around the Nyquist frequency) or exploit other properties of the input signal. Blind calibration techniques, which don’t use a reference channel, are suitable for correction of commercial TI-ADCs, or TI-ADC systems using commercial ADCs as channels. Techniques employing additional channels require a more complex layout (especially for the clock tree) and need an additional ADC, whose overhead cost is significant, especially for 2- or 4- channel TI-ADCs. However, we show that the estimation process is faster and more accurate when a reference channel is present, and many different error models can be used (exploiting different points in the accuracy / complexity trade-off).

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about $1.5\,\, {\times } \,\, 10^{6}$ samples for the calibration of five stages.

A novel digital calibration technique to correct DAC errors from capacitor mismatch is presented in this paper. The jump height of transfer curve is measured for calibration and random interference introducing method helps to improve the measurement accuracy with seldom modification on analog circuits. An 11-bit 250Ms/s subrange ADC based on SAR architecture is designed to test this calibration technique. Simulation results show that significant improvements can be achieved with the proposed calibration technique.

This paper presents a new digital calibration scheme for pipelined ADCs. The proposed technique corrects the gain error of the converter. Analog and digital complexity required in the correction process resembles the correlation based method; however the new method converges many times faster. The high speed of convergence is due to the use of frequency characteristics, instead of correlation process, to separate injected signal from the input signal. The proposed technique was compared to one of the fastest correlation based methods (FGEC). Simulation results show that the speed of the proposed algorithm is the same as FGEC without the need for interpolation which is needed in FGEC method.

Time-Interleaved Analog-to-Digital Converter (TIADC) is a promising approach to meet the requirement of high speed wireless communication systems. However, mismatches between the channels of TIADCs generate unwanted distortions at the output spectrum. This paper demonstrates a fully digital background calibration technique to identify and compensate three all deviations which are offset, gain and timing mismatches for TIADCs. In which, offset mismatch is corrected by computing the average of the output samples of each channel. The gain and timing mismatches are compensated by using LMS algorithm and the modulation matrix m[n]. The simulation results show that the performance of the ADC is improved by 41.32 dB for SNDR and 64.6 dB for SFDR.

A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.

A new digital background calibration technique to compensate the capacitor mismatch in pipelined analog-to-digital converters (ADC) is presented. A digital signal from the ADC output is constructed so as to transform the capacitor mismatch to global gain error. A simple modification to the conventional MDAC allows the ADC to toggle between different configurations to create a reference signal used to calibrate blindly the ADC. This method does not produce any limitation of the ADC in terms of speed or input dynamic range.