Design and application of RISC processor

Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. The advanced RISC microprocessors are extensively used for many of the complicated systems. Reduced Instruction set Computing (RISC) is a CPU (Central Processing Unit) design mechanism that displays fundamental instruction set and performs better after comparison with the other microprocessor architecture and has the ability to perform commands per instruction through microprocessor cycles. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. Building of a fully synthesizable 32-bit RISC processor with Fetching unit, Decoding unit, Data and instruction memory, and Execution unit. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using I-sim. A 32-bit RISC is simulated and checked through VIO IP cores. We can use debug feature to drive and monitor signals that are present on the real hardware. This work is intended with Verilog HDL and implemented with the help of development board using Artix-7 FPGA device. The outcomes of performance are evaluated in terms of area, timing performance and maximum frequency of operation. The RISC processor compares earlier comparable architecture with efficient developments.

Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. A 16 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx ISE 14.7 design suite. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. In addition to these blocks, designed RISC Processor consists of other blocks like Control unit and data path, Register Bank, Program Counter and Memory. The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that 44% savings in power in case of MAC and that of 12% in case of ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced by 45% in case of MAC and that of 35% in case of ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay by 34% and saves around 88% power compared to conventional processor. Hence the improvement in speed of operation, reduction in power utilization and less area utilization are the key features of designed RISC processor.

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim. Reduced Instruction Set Computers (RISCs) are now use for all type of computational tasks. In the area of scientific computing, RISC workstations are being increasingly used for compute task such as DSP, DIP etc. RISC concepts help to achieve given levels of performance at significantly lower cost than other systems. Pipelined RISC improves speed and cost effectiveness over the ease of hardware description language programming and conservation of memory and RISC based designs will continue to grow in speed and ability. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 4-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. The architecture supports 8 instructions to support Arithmetic, Logical, Shifting, and load -store operations. Verilog HDL has evolved as a standard hardware description language. A hardware descriptive language is a language used to describe a digital system. HDL's allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology- independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description for the circuit. The simulator which is used for the language is Xilinx ISE and Modelsim. Verilog is capable of describing simple behaviour. Machine cycle instructions allow the processor to handle several instructions at the same time. The processor can work at a high clock frequency and thus yields higher speed. This paper is about design of a simple RISC processor and synthesizing it. The RISC architecture follows single-cycle instruction execution.

Over the past 11 years, the Air Force Research Laboratory (AFRL), Phillips Research Center (formerly Phillips Laboratory) has championed the development of microprocessors and computers for United States Air Force (USAF) space and strategic missile application. The latest of these programs, the Advanced Technology Insertion Module (ATIM), is currently scheduled for completion at the end of 1997. ATIM is developing two single-board computers based on 32-bit reduced instruction set computer (RISC) processors. ATIM technology is baselined in the majority of today's Department of Defense (DoD), NASA, including Mars Pathfinder, and commercial satellite systems. The Improved Space Computer Program (ISCP) is envisioned as the next-generation space computer: merging advanced technologies and architectures to meet the high-performance, on-board processing needs for 21/sup st/ century DoD, NASA, and commercial satellites. ISCP is a three pronged effort to evaluate evolving mission requirements, develop a commercial-heritage architecture, and integrate emerging technologies for space applications. These three areas are: the Phase I Concept/Architecture Studies, the Improved Space Architecture Concept (ISAC), and the technology development efforts. ISAC lays out a sequential approach aimed at developing and demonstrating the potential for on-board, satellite processing. The combined serial and parallel development activities will prove that commercial-heritage architectures and technologies can reduce the development time and costs associated with building the next-generation spacecraft.

Chapter 11 - The ARM Architecture

Hardware software co-design plays a crucial part in the embedded processor development especially with the current advancement of reconfigurable platforms. The reconfigurability features offered by platforms such as Field Programmable Gate Array (FPGA) has permitted the modification of the internal processor architecture with lower cost and higher performance. While the hardware architecture could be changed through various methods, the modifications need to be complemented with a compatible assembler that suits the amended architecture. This paper presents a two-pass assembler design technique that adapts to any instruction set architecture (ISA) modifications being applied on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to include new instruction sets. The assembler is developed based on two-pass approach and the assembling process would generate a coefficient file that is used as initialization files during the FPGA implementation of the processor core. The assemblers have been successfully developed with correct output format and verified during the FPGA implementation using Xilinx Spartan-3AN board.

This research paper presents design & simulation of a high performance five stage pipelined 8 bit or 16-bit Microprocessor without Interlocked Pipeline Stages (MIPS), which is a Reduced Instruction Set Computing (RISC) architecture based processor. The purpose of RISC microprocessor is to execute a minuscule batch of instructions, with the intention of proliferating the celerity of the processor. This processor was designed with 5 phases of pipeline in particular Instruction Fetch (IF), Instruction Decode & Register Fetch (ID), Execution & Address Calculation (EX), Memory Access (MEM) and Write Back (WB) modules. The designing process was done using a myriad of modules which are the ALU, Control Unit, Program Counter, MUX, Instruction Memory, Data Memory, CPU, Register File, and Sign Extension. The Proposed design is developed by Verilog HDL and Simulated by Modelsim 6.4 c and Synthesized by Xilinx tool and proposed system implemented in FPGA Spartan 3 XC3S 200 TQ-144.

The embedded systems have received increasing research interest in recent years due to its wide usage. This paper presents system on programmable chip (SOPC), a new technology in the embedded systems, to support the development of design projects for undergraduate students in their electrical and computer engineering curriculum. FPGA-based SOPC development board with reduced instruction set computer (RISC) processor cores, a top-down design approach with FPGA computer-aided design tools, a C compiler for the RISC soft-processor core and a large FPGA with on-chip memory are used for a wide variety of student design projects. The course, which includes both software and hardware, can meet the different needs of students from different professional backgrounds and contribute to a better understanding between electrical engineering and computer science and therefore can increase the competitiveness of students.

Register array processor

Omega - A RISC Architecture for Real-Time Applications

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...

The evolution of computer architecture has given rise to two main approaches: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). These architectures differ significantly in terms of instruction design, efficiency, and performance. This study aims to analyze the performance and efficiency of RISC and CISC in the context of computer architecture organization. The methodology includes a literature review, comparative analysis, and performance evaluation based on parameters such as processing speed, power consumption, and design complexity. The results indicate that RISC tends to be more efficient in terms of power consumption and execution speed for simple instructions, while CISC excels in handling complex instructions with fewer lines of code. The findings of this study can serve as a reference for the development of modern computer architectures that balance performance and efficiency.

Reduced instruction set computer (RISC) processors are built on the philosophy of eliminating complex instructions and of limiting the instruction set to only simple operations, thereby emphasizing fast execution. This approach has been adopted in many modern processors. Extending the RISC concept even further, we propose mono instruction set computer (MISC) architecture, which constrains the number of instructions on a processor to a single instruction. Because a MISC processor contains only a single instruction, in order to execute a variety of instructions, MISC processors must be implemented onto a programmable architecture and its configuration must be done frequently. Existing FPGAs can not achieve a high-performance MISC processor due to their long reconfiguration time. Therefore, we have been developing an optically reconfigurable gate array (ORGA) that supports high-speed dynamic reconfiguration. The ORGA can realize an ideal platform for MISC processors. In this research, we designed MISC processors based on RISC-V processor using the high-level hardware description language FSL. The design has been implemented onto an FPGA. This paper presents the evaluated results.

The design of Multiplier-Accumulator (MAC) unit can be implemented by using the Vedic multiplier along with the reversible logic gates. The designing of Vedic multiplier is designed by using the new sutra called “Urdhava Triyagbhayam”. The performance of the MAC operation depends on the multiplier unit and the adder units. Here the designing of a multiplier and an adder can be designed by using the reversible gates to get the high speed of operation and also a Vedic multiplier is used for the higher performance, lesser area and to reduce the partial products. Nowadays reversible computing will take a more preferable for low power dissipation, higher speed of operation. Here, we proposed an 8, 16, 32, 64-bit Vedic multiplier is designed by using the carry save adder(CSA), the kogge stone adder(KSA) and the DKG adder out of these the proposed DKG gate adder is having the high speed of operation. The comparative analysis is carried out among the ripple carry adder (RCA), carry save adder, kogge stone adder. Finally, it has been proved that the proposed DKG gate with Vedic multiplier-adder is having the high speed of operation. The overall Simulation and synthesis process is carried out with Xilinx ISE 14.7 and is dumped on the FPGA Zynq board.

In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.