Design of 16 Bit RISC Processor and Implementation using MIPS Technique

Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. The advanced RISC microprocessors are extensively used for many of the complicated systems. Reduced Instruction set Computing (RISC) is a CPU (Central Processing Unit) design mechanism that displays fundamental instruction set and performs better after comparison with the other microprocessor architecture and has the ability to perform commands per instruction through microprocessor cycles. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. Building of a fully synthesizable 32-bit RISC processor with Fetching unit, Decoding unit, Data and instruction memory, and Execution unit. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using I-sim. A 32-bit RISC is simulated and checked through VIO IP cores. We can use debug feature to drive and monitor signals that are present on the real hardware. This work is intended with Verilog HDL and implemented with the help of development board using Artix-7 FPGA device. The outcomes of performance are evaluated in terms of area, timing performance and maximum frequency of operation. The RISC processor compares earlier comparable architecture with efficient developments.

Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. A 16 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx ISE 14.7 design suite. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. In addition to these blocks, designed RISC Processor consists of other blocks like Control unit and data path, Register Bank, Program Counter and Memory. The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that 44% savings in power in case of MAC and that of 12% in case of ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced by 45% in case of MAC and that of 35% in case of ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay by 34% and saves around 88% power compared to conventional processor. Hence the improvement in speed of operation, reduction in power utilization and less area utilization are the key features of designed RISC processor.

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim. Reduced Instruction Set Computers (RISCs) are now use for all type of computational tasks. In the area of scientific computing, RISC workstations are being increasingly used for compute task such as DSP, DIP etc. RISC concepts help to achieve given levels of performance at significantly lower cost than other systems. Pipelined RISC improves speed and cost effectiveness over the ease of hardware description language programming and conservation of memory and RISC based designs will continue to grow in speed and ability. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 4-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. The architecture supports 8 instructions to support Arithmetic, Logical, Shifting, and load -store operations. Verilog HDL has evolved as a standard hardware description language. A hardware descriptive language is a language used to describe a digital system. HDL's allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology- independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description for the circuit. The simulator which is used for the language is Xilinx ISE and Modelsim. Verilog is capable of describing simple behaviour. Machine cycle instructions allow the processor to handle several instructions at the same time. The processor can work at a high clock frequency and thus yields higher speed. This paper is about design of a simple RISC processor and synthesizing it. The RISC architecture follows single-cycle instruction execution.

An effective and flexible photo-printing controller for D2T2 (Dye Diffusion Thermal Transfer) and photo inkjet is proposed. The objectives of the present work are to develop the controller architecture using RISC (Reduced Instruction Set Computer) processor and its middle-ware especially used for uniformity correction. In present architecture, the middle-ware provides functional compatibility in the middle layer between hardware and application software.

Finally, the integration of these individual components culminates in the execution of the complete MIPS datapath. The MIPS (Microprocessor without Interlocked Pipeline Stages) architecture serves as a widely recognized and utilized instruction set architecture. Implementing the complete datapath involves orchestrating the flow of instructions through the CPU, from instruction fetch to execution and memory access, showcasing the culmination of our efforts in crafting a functional and efficient processor. In essence, this project not only provides a hands-on experience in HDL-based digital design but also immerses us in the intricacies of CPU architecture, emphasizing the importance of each component in achieving a harmonious and high-performance computing system

In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.

Today the microprocessor industry has come a long way from Intel 4-bit microprocessor 4004 to multicore processors. The industry has kept growing consistently with advancements in Very Large Scale Integration (VLSI), multicore processor architecture and other breakthroughs. But soon a limit will be reached as to how far we can squeeze transistors onto a chip. The steady growth in computing power will decline necessitating new breakthroughs in technology. Asynchronous microprocessor architecture might be one such way. This study describes a delay based design approach for a 4-bit asynchronous microprocessor. Delay blocks with delays marginally more than the executing blocks are used in conjunction to generate a ready signal to the Control Unit (CU). This ready signal is used by the control unit to determine the completion of current execution and signal the next execution block. Individual blocks like Program Counter (PC), Arithmetic Logic unit (ALU), instruction decoder and registers were designed and implemented in Very high-speed integrated circuit Hardware Description Language (VHDL). Basic design blocks were also tested on Altera DE0 Field Programmable Gate Array (FPGA) board.

The authors describe the VL86C010 family of RISC (reduced-instruction-set computer) processors and peripherals, which was originally a custom design for Acorn Computers Ltd. The resultant performance proved its value in many other functions as well, providing an ASIC (application-specific integrated circuit) core. The VL86C020 provides an ASIC-capability two-and-a-half times performance increase over the previous generation VL86C010 while maintaining software compatibility. By offering the CPU and cache memory on a single device, and itself as a core, the processor offers a superior upward migration path because the highest-frequency memory path is not required to cross a chip boundary. As process rules continue to shrink, the clock frequency can be increased for on-chip operations accordingly without making undue demands on external memory system bandwidth. >

This paper presents the design of multi-cycle 32-bit Reduced Instruction Set Computer (RISC) processor for better performance and higher speed of operation. The processor is capable of executing more number of instructions with simple design and less critical path delay. The designed processor was simulated and synthesized using Xilinx 14.7 ISE design suite. The processor executes each and every instruction in more than one cycle that's why the term multi-cycle. Each instruction is divided into three main states namely the Fetch state, the Decode state and the Execution state. The first two sates remain the same for all the instruction the last state, however depends on the type of operation performed in that instruction.

Hardware software co-design plays a crucial part in the embedded processor development especially with the current advancement of reconfigurable platforms. The reconfigurability features offered by platforms such as Field Programmable Gate Array (FPGA) has permitted the modification of the internal processor architecture with lower cost and higher performance. While the hardware architecture could be changed through various methods, the modifications need to be complemented with a compatible assembler that suits the amended architecture. This paper presents a two-pass assembler design technique that adapts to any instruction set architecture (ISA) modifications being applied on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to include new instruction sets. The assembler is developed based on two-pass approach and the assembling process would generate a coefficient file that is used as initialization files during the FPGA implementation of the processor core. The assemblers have been successfully developed with correct output format and verified during the FPGA implementation using Xilinx Spartan-3AN board.

Compiler-assisted power optimization for clustered VLIW architectures

This paper presents an Application Specific Instruction-set Processor (ASIP) for the realization of Hard Disk Drive Regular Servo Sequencer (RSS) and the related firmware for its reconfiguration. The proposed architecture is a 12 bit Reduced Instruction Set Computer (RISC) processor with 32 registers, Harvard architecture memory and 19 I/O ports. The Instruction Set has been customized to Regular Servo Sequencer. The firmware can reconfigure the Microprogrammed Servo Sequencer (MSS): itpsilas possible to initialize registers and instruction memory and to reconfigure the port mapping. The target is to gain more flexibility than hardwired Regular Servo Sequencer, but at the same time to maintain the same performance in terms of elaboration frequency. The performance of the proposed architecture achieved by cell-based synthesis software is reported.

12 - The next generations

This paper presents a new pyramidal architecture FPGA (PARC) including a RISC processor dedicated for fast dynamic configurations systems. The PARC FPGA consists of a large number of fine-grained array of optimized heterogenous logic blocks and a new pyramidal structure with three hierarchical levels. The proposed FPGA is a reprogrammable SRAM based device. The built-in processor is designed as a 16-bit microprocessor with a reduced instruction set (32 instructions), hardware and software interrupts, and 16-bit address and data buses. The whole device has been developed with Synopsys design automation CAD tools, using VHDE and the 0.8 /spl mu/m BiCMOS technology from Nortel to operate at a 50 MHz clock frequency.

Energy efficiency has become one of the most important topics in computing. To meet the ever increasing demands of the mobile market, the next generation of processors will have to deliver a high compute performance at an extremely limited energy budget. Wide single instruction, multiple data (SIMD) architectures provide a promising solution, as they have the potential to achieve high compute performance at a low energy cost. We propose a configurable wide SIMD architecture that utilizes explicit datapath techniques to further optimize energy efficiency without sacrificing computational performance. To demonstrate the efficiency of the proposed architecture, multiple instantiations of the proposed wide SIMD architecture and its automatic bypassing counterpart, as well as a baseline RISC processor, are implemented. Extensive experimental results show that the proposed architecture is efficient and scalable in terms of area, performance, and energy. In a 128-PE SIMD processor, the proposed architecture is able to achieve an average of 206 times speed-up and reduces the total energy dissipation by 48.3 % on average and up to 94 %, compared to a reduced instruction set computing (RISC) processor. Compared to the corresponding SIMD architecture with automatic bypassing, an average of 64 % of all register file accesses is avoided by the 128-PE, explicitly bypassed SIMD. For total energy dissipation, an average of 27.5 %, and maximum of 43.0 %, reduction is achieved.