Design and Implementation of I2C Bus Protocol on Master and Slave Data Transfer Based on FPGA

Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is to design prototype of an input/output port with handshaking capability using Field Programmable Gate Array (FPGA). The main reason of using the FPGA technology is it has unlimited number reprogrammed, cuts developing cost and development time. Xilinx Foundation 2.1i Series software in VHDL description was used as a development tool in this project. The VHDL codes were assimilated into a design and development atmosphere to accomplish many subtasks such as FPGA synthesis, optimization, placement, and routing. The successful design was translated, mapped, routed, and placed onto FPGA Demo Board. XC4010XLPC84 Xilinx FPGA from XC4000XL family was used as a target board. In prototype design, the FPGA pins were connected to a parallel printer port by using a coupled 25-pin DB connector, with a 36-pin Centronics connector cable. The output signals were observed and analyzed by using a logic analyzer.

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD’s prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

Software defined radio (SDR) is a vast and emerging field that requires the design of various technologies such as antenna, RF, IF, and digital baseband subsystems. Among all these technologies, data converters that convert signals between analog and digital domains are highly crucial. On the other hand field programmable gate arrays (FPGAs) based platforms are being preferred for evaluating and implementing the digital communication concepts due to their programmability and reconfigurability. As a result they are well suited for the design of SDR technology. In this research work, we develop a platform where high-speed data converters are interfaced with high performance FPGAs. Interfaces are designed for analog-to-digital convertors (ADC) and digital-to-analog convertors (DAC) to communicate with FPGAs. For the interface design between ADC and FPGA, a double data rate and a low voltage differential signalling based serial output is adopted. And, for the interface design between DAC and other FPGA, parallel complementary metal oxide semiconductor outputs are used. To reconfigure the modes and parameters of the data convertors, serial peripheral interface data controllers have been designed. We have through simulations evaluated the performance of our designed interfaces between data convertors and FPGAs.

SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace‐back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi‐core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145 × speedup over the naive CPU version on a quad‐core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65 Mbps and 12 × speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7 × speedup over Intel quad‐core CPU i5‐2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix‐4 pipelined architecture for the TVDA in a 45‐nm FPGA chip from Xilinx (XC6VLX760). Under 209.15‐MHz clock rate, it achieves a throughput of 418.30 Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real‐time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright © 2013 John Wiley & Sons, Ltd.

Scene classification from images is a challenging problem in computer vision due to its significant variability of scale, illumination, and view. Recently, Latent Dirichlet Allocation (LDA) model has grown popular in computer vision field, especially in scene labeling and classification. However, the effectiveness of the LDA model for the scene classification has not yet been addressed thoroughly. Especially, there is little experimental evaluation on the model's performance for different types of features. Fusion of multiple types of features is usually necessary in the scene classification due to the complexity of scene images. In this paper, we investigate the effectiveness of the LDA model in scene classification by using 7 types of features (i.e. uniform grid based interest points, Harris corner based interest points, scale invariant feature transform (SIFT), texture, shape, color, and location) and their various combinations. Furthermore, we compare the performance of the LDA model with Support Vector Machine (SVM) classifier. All experiments are performed on the UIUC Sport Scene database. The experiments demonstrate that the performance of the LDA model 1) is significantly lower than the SVM classifier for the scene classification over different types of features; and 2) decreases by fusing multiple features while improvement shown in SVM classifier.

Compared with the four-phase optical structure, the grating encoder based on two-phase optical structure reduces the number of optical devices used in the system and makes the system more compact. Due to the high requirements for realtime and parallel processing of algorithm solution, the powerful parallel computing ability of Field Programmable Gate Array (FPGA) and customized hardware acceleration algorithm are needed to improve the real-time performance. In the previous research, the displacement signal generated by the grating encoder can be input into the FPGA through analog to digital converter (ADC) sampling, and then complete self-designed filter filtering, phase correction and displacement solution. In this paper, further, the ADC sampling rate adjustable interface is added to the FPGA, the global signal and the dc offset remove algorithm is added, and the displacement solution results in the form of fixed-point number are output to the host computer through the MicroBlaze (MB) soft core. MB core can realize process control and interface conversion on FPGA, and use a small amount of logic resources to replace the functions of MCU and DSP of traditional embedded measurement system, so as to further improve the integration of the instrument. A series of experiments are carried out on the two-phase FPGA platform. ADC sampling rate is 200ksps, 8-Channel synchronous parallel sampling, FPGA system clock frequency is 200MHz. The linear displacement table is set to drive the measurement grating at different displacement speeds, and the total stroke is set to 10mm. The FPGA real-time displacement solution platform is tested. The experimental results show that FPGA obtains accurate displacement solution results under different speed tests. In the test of 2 mm/s, the maximum cumulative displacement measurement error is 5um, which shows the real-time performance and accurate displacement solution performance of FPGA platform.

Feature-rank-code-based classifiers have been proposed recently in order to reduce the complexity for electronic nose system (ENS). The performance of these classifiers is degraded when the discriminatory information of gases lie in the actual feature values not in the ranks of features. To overcome the problem, a gas identification system based on a simple distance measure in combination with different type of features is proposed. In order to improve the computational cost of the existing ENS, a novel combination of optimum subset of features is proposed. To achieve the aim of low computational cost, a large feature vector is recursively reduced to a small number of features without compromising the classification accuracy of the system. Discrete binary particle swarm optimization, a metaheuristic for global search is used in a recursive setup to select the optimum subset of features for classification. Euclidian distance is used as a similarity measure for identification of different industrial gases. The proposed system is tested for the identification of 13 different industrial gases, namely, C3H8, Cl2, CO, CO2, SO2, NO2, NH3, C2H4O, C3H6O, C2H4, C2H6O, C7H8, and CH4. These gases are contained in three different data sets; two among these data sets are acquired experimentally in a laboratory setup, while one of these data sets is taken from the University of California at Irvine machine learning repository. Results reveal that the computational cost and the memory requirement of an ENS can be significantly reduced by combining different type of features. An average classification accuracy of 98.17% is achieved by the proposed system with an average 69.04% reduction in memory requirement using only three to five features.

A multi-ensemble method based on deep auto-encoders for fault diagnosis of rolling bearings

This paper presents new results on an innovative approach for solving satisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field Programmable Gate Arrays (FPGAs). This approach has become feasible due to recent advances in Reconfigurable Computing, and has opened up an exciting new research field in algorithm design.We have developed an algorithm that is suitable for a logic circuit implementation. This algorithm is basically equivalent to the Davis-Putnam procedure with Experimental Unit Propagation. The algorithm requires fewer hardware resources than previous approaches. Simulation results show that this method can solve a hard random 3-SAT problem with 400 variables within 1.6 minutes at a clock rate of 10MHz. Faster speeds can be obtained by increasing the clock rate. Furthermore, we have actually implemented a 128-variable, 256-clause problem instance on FPGAs.

Over the course of 60 years, since the invention of the integrated circuit (IC), exponential improvements in cost, performance and power consumption were observed. Such advances have been strongly linked with the continuous reduction of the dimensions in manufactured ICs, but this trend has shown decreasing benefits as fundamental limits are reached. Notice that such tiny devices have increased variability, which generates unpredictable variations in the behavior of the manufactured devices. These uncertainties are typically addressed by defining margins on the clock period, estimated during the design phase. However, the overly conservative margins produce significant degradations in performance. Additionally, the evolution that enabled circuits with increasingly higher density of components, also resulted in an extremely complex IC design. At every step, electronic design automation (EDA) tools are challenged to handle this increasing complexity, requiring more powerful techniques to comply with the specification constraints within an affordable runtime. This thesis investigates alternatives in order to improve power, performance, area, and cost, using established IC manufacturing technologies. Advances in EDA are proposed in three distinct topics: area minimization using Boolean methods, area and delay reduction for designs based on fieldprogrammable gate array (FPGA), and an alternative clocking scheme to reduce timing margins. The first contribution consists of a technology-independent method for area minimization of combinational logic. Local optimization is applied on and-inverter graphs (AIGs), performing multi-output Boolean decomposition using two-literal divisors, targeting node count reduction. The second contribution regards two methods targeting technology mapping of FPGAs. On one hand, a functional decomposition approach, which uses the support size as cost function, exploring the inherent characteristics of FPGAs. On the other hand, an approach for recursive remapping, which reduces the structural bias of the subject graph, uses the mapping results as cost function, and obtains significant reductions in area and delay. The third contribution evaluates the dynamic variability mitigation and simplification of power delivery networks (PDNs) using an adaptive clocking scheme based on ring oscillator clocks (ROCs). The impact of the PDN parameters and ROC location is investigated, showing potential improvements in performance, leakage power and cost. A lo largo de los 60 años desde la invención del circuito integrado (CI), se han producido mejoras exponenciales en su coste, rendimiento y consumo de energía. Ese progreso esta fuertemente vinculado a la reducción continua de las dimensiones de fabricación de los circuitos integrados, pero esta tendencia ha ido mostrando menos beneficios a medida que se alcanzan límites fundamentales. Estos dispositivos minúsculos tienen una mayor variabilidad, lo que genera variaciones impredecibles en el comportamiento de los dispositivos fabricados. Estas incertidumbres generalmente se abordan mediante la definición de márgenes en el período de reloj, estimado durante la fase de diseño. Sin embargo, márgenes excesivamente conservadores producen degradaciones significativas en el rendimiento. Además, la evolución que permitió crear circuitos con una densidad de componentes cada vez mayor, también incrementado la complejidad de los CI. En cada paso del proceso de diseño, las herramientas de automatización de diseño electrónico (EDA) se enfrentan al desafío de manejar esta complejidad creciente, lo que requiere técnicas más potentes para cumplir con las restricciones impuestas por las especificaciónes dentro de un tiempo de ejecución asequible. Esta tesis investiga alternativas para mejorar el consumo de energía, el rendimiento, el área y el coste, utilizando las tecnologías de fabricación de CI ya establecidas. Los avances en EDA se proponen en tres temas distintos: minimización de área usando métodos booleanos, reducción de retardo y área para diseños basados en matrices de puertas programables (FPGA), y un esquema de reloj alternativo para reducir los márgenes de tiempo excesivamente conservadores. La primera contribución consiste en un método independiente de tecnología para minimizar el área de la lógica combinacional. Se aplica optimización local en grafos de AND-inversor, utilizando una descomposición Booleana de múltiples salidas con divisores de dos literales, con el objetivo de reducir la cantidad de nodos. La segunda contribución propone dos métodos para el mapeo tecnológico de los FPGA. Por un lado, un método de descomposición funcional, que utiliza el tamaño del soporte como función de coste, explorando las características inherentes de los FPGA. Por otro lado, un método de mapeo recursivo, que reduce la distorsión estructural del grafo sujeto, utiliza los resultados del mapeo como función de coste y obtiene reducciones significativas en área y retardo. La tercera contribución evalúa la mitigación de la variabilidad dinámica y la simplificación de la red de suministro de energía (PDN) utilizando un esquema de reloj adaptativo basado en un oscilador en anillo (ROC). Se investiga el impacto de los parámetros de la PDN y la ubicación del ROC, mostrando mejoras potenciales en el rendimiento, consumo estático y coste.

The paper addresses the potential benefits of using a field programmable gate array (FPGA) as opposed to a traditional processor for music synthesis. The benefits result from the use of a cellular design, with each cell performing identical operations on its own state and the states of its neighbours. This gives advantages of design simplicity through inherent parallelism. A cellular model which has previously been used for music synthesis is the mass spring paradigm, and this model is implemented on an FPGA. On a sequential processor, the clock speed requirements of this model increase as N2 (where N is the number of cells), whereas the clock speed requirement increases as N on an FPGA (if the cells can be made small enough that available area on the chip is not a constraint). To make the cells small enough, a bit-serial design was used. This work was performed to advocate the FPGA as a stand-alone live performance music synthesis platform, which has the potential to be reconfigured for example in performance, between synthesis techniques as different sound patches are selected. The paper considers in particular the mass-spring model, because it demonstrates the type of music synthesis technique for which FPGAs provide the greatest potential benefit. The capability to reconfigure combined with the high performance that can be achieved using cellular design suggests that the FPGA is an ideal platform for a live performance hardware music synthesiser, combining the flexibility of software with the speed of a custom ASIC.

Adaptive filters are prevalent in many real‐time signal processing applications. Many adaptive algorithms already exist, but most of them assume white Gaussian noise as disturbance. However, for many applications such as electrocardiogram, foetus heart rate measurement, low frequency atmospheric noise, underwater acoustic noise and signal measurement in instrumentation, the impulsive noise is more common. This study presents a modified robust mixed norm (MRMN) adaptive filter algorithm robust to impulsive noise with higher convergence rate and lower steady state error (SSE). MRMN adaptive filter algorithm has been simulated using Matlab and Xilinx system generator high level synthesis tool and a significant improvement in SSE and convergence speed is obtained compared with the existing adaptive filter algorithms for similar specifications. The proposed algorithm is also described using VHDL and synthesised using Xilinx synthesiser tool in order to implement on field‐programmable gate array (FPGA). The FPGA post route and place implementation results show nearly 90% reduction in resource utilisation and nearly 2.6 times improvement in clock frequency as compared with the existing FPGA based implementation for similar specifications.

The wave union (WU) method can improve the performance of time-to-digital converters (TDCs) without consuming additional logic resources, and has therefore been widely adopted in field-programmable gate array (FPGA)-TDC designs. However, the propagation requirement of the WU pulse train forces the tapped delay line (TDL) to span longer than one clock period, such that conventional encoders must introduce extra dead time to ensure correct decoding. This article presents a low-deadtime, high-precision FPGA-based TDC that combines a 4edge WU-A scheme, dual sampling, and a resource-efficient event-aggregation encoder. With the proposed eventaggregation encoding, the WU edge positions associated with different events on the TDL are aggregated and encoded with negligible additional FPGA logic-resource usage, reducing the dead time of WU-based FPGA-TDCs to one clock cycle. In addition, to address the more severe bubble errors in advanced FPGA technology nodes, we apply clock-skew-aware placement constraints to optimize the TDL clock distribution. For the first time, a 4-edge WU-A TDC is implemented within a single clock region on a 16nm UltraScale+ FPGA. The optimized design achieves an equivalent bin width of 0.9 ps and an equivalent quantization error of 0.26 ps, improving the measured timing precision to 1.45-2.19 ps.

A high-performance framework for a network programmable packet processor using P4 and FPGA