Design and implementation of reconfigurable coders for communication systems

Dynamic partial reconfigurable Viterbi decoder for wireless standards

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

In order to realize lower power consumption multi-Gbps communications terminals in 60 GHz, this paper proposes a single carrier with FEC (Forward error correction) communications system together with a beam tracking and switching receiver antenna. In the proposed system, communications path will be switched from the LOS (line of sight) path to one of the best S/N path when the LOS path is interrupted by a moving object such as human body and continue the communications. The advantage of the proposed system is to have smaller delay spread that will make no necessity of OFDM (Orthogonal Frequency Division Multiplexing) as a tool to mitigate huge delay spread which is commonly observed in WLAN (Wireless LAN) systems. To validate the proposed system, this paper took the channel models created by IEEE802.15.3c std. in that TX and RX antennas are facing each other and reflected waves are received from all directions (360 degrees) at the RX antenna. The difference created on top of the TG3c channel model is to track and switch the RX antenna to the best S/N reflected wave when the system lost the LOS path. In this way, much smaller delay spread is expected in the proposed system which will lead to no necessity of OFDM signal transmission. The computer simulation results show bit error rate performances of the proposed system has very little degradation by applying strong FEC of “convolutional encoding and Viterbi decoding”, leading to potential necessity of equalizer for further bit error rate improvement but no necessity of OFDM signal transmission. Thus, the proposed system is good for multi-Gbps transmission over low power consumption portable terminals in 60 GHz.

An algorithm for generating random binary data, convolutional encoding the data, passing the encoded data through a noisy channel, quantizing the received channel symbols, and performing Viterbi decoding on the quantized channel symbols to recover the original binary data is implemented in MATLAB using built-in functions in Communications Toolbox. The developed tool will be used in the educational process in the course Channel coding in telecommunications systems and it will enable students to comprehend the principles of convolutional encoding and Viterbi decoding.

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.

The authors propose a novel control channel quality improvement scheme for satellite communication systems using a majority decision method over convolutional coding and Viterbi decoding channels. To improve majority decision performance, which is degraded by burst errors due to Viterbi decoding in conventional serial transmission methods, a parallel transmission method is proposed. The performance of the parallel and serial transmission methods has been analyzed, and experimenta have been carried out using rate 1/2 convolutional encoding and Viterbi decoding (constraint length 4 and 7). It is shown that the parallel transmission method has about 10/sup 10/ times lower block error performance at P/sub e/=1*10/sup -4/ than the conventional method. >

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

This paper describes the implementation of the scaleable channel coding scheme (Annex C) for ITU-T G.723.1 speech coder. Speech parameter bits from the encoded frame are reordered and allocated to bit classes of differing sensitivity. Each class is then coded by a rate compatible punctured convolutional code. A rate control algorithm provides scaleability by determining the number of bits and the puncture code per class according to the available channel capacity and speech frame type. At the receiver the bitstream is decoded and errors corrected by a Viterbi decoder and the recovered bitstream reordered back into the original speech frame parameters. Flags, which are generated depending on the error conditions, are passed to the speech decoder to enhance error concealment thereby improving the perceptual performance for the listener. A real-time DSP implementation of this scaleable channel coder is presented. The system is implemented on a TMS320C5X fixed-point DSP chip and integrated together with the speech codec. Efficient architectures are used for implementing the rate control algorithm, convolutional encoder and Viterbi decoder.

This study evaluates the error resilience performance of a MIMO system combining Alamouti space time block coding (STBC) with convolutional encoding and Viterbi decoding. The proposed architecture integrates spatial diversity with temporal redundancy, providing robustness against both multipath fading and additive noise. Simulation results demonstrate the high potential of this approach for fifth generation communication systems and Wi-Fi 6/7, where high reliability and moderate computational complexity are simultaneously required.

An efficient and hardware economic channel coding technique is essential in high-speed mobile communication systems. The channel coding parameters will have a large impact on the system performance (data rate and bit error rate) and also on the hardware development in terms of area consumption and timing behaviour. Therefore, important system parameters like code rate, constraint length and Viterbi decoding strategy (single state or best state and the resulting truncation depth for both strategies) have to be decided early in the design flow. The objective of this paper is to discuss the technical tradeoff (system performance and hardware cost) when choosing the channel coding parameters for a system with convolutional encoding and Viterbi decoding. For a wide range of possible channel coding parameters the impact on the system performance and on hardware consumptions, which have been acquired from field programmable gate array (FPGA) implementations, are discussed and compared.

Application specific integrated circuits are used to provide real-time performance of handheld devices within the compact physical size and low energy dissipation. However, these circuits are inflexible for any modification like redesign and refabrication. Reconfigurable architectures are promising alternative for conventional computing devices such as application-specific integrated circuits. It provides high-level flexibility to adapt the applications through dynamic hardware customization even after fabrication. A reconfigurable computing system design considers the peculiarities of the targeted application domain along with architectural issues like dynamic reconfiguration, partial reconfiguration, hardware/software co-design and context management. A brief survey has been carried out to understand the concepts and applications of CGRA, FPGA, SoC, NoC, MPSoC, dynamic partial reconfiguration, hardware/software co-design, design-space exploration, multi-objective optimization, genetic algorithm and reconfigurable computing on wireless communications. This paper deals with the survey on modeling, design, implementation and evaluation of coarse-grained dynamically reconfigurable processor architectures targeting the real-time embedded computing domain.

SIMD processors are increasingly used in embedded systems for multi-media applications because of their area- and energy-efficiency. Communication between the processing elements (PEs) in an SIMD processor has remained a cause of inefficiency however; the SIMD concept prescribes that all PEs communicate in the same clock cycle. Existing SIMD architectures solve this problem either by multi-hop communication (causing cycle overhead), or by a fully connected communication network (causing area overhead). To solve the communication bottleneck, we propose a reconfigurable SIMD architecture (RC-SIMD) with a set of delay-lines in the instruction bus, distributing the accesses to the communication network over time. We can (re-) configure the size and number of delay-lines, a specific configuration representing a trade-off between the number of clock cycles and the length of a clock period. Reconfiguration time is typically much less than 1% of the execution time of an algorithm, and the extra configuration hardware is less than 2%. Experiments show that our reconfigurable architecture achieves (on average) more than 10% performance improvement over a non-reconfigurable architecture.

Data transmission over the wireless transmission channel is adversely affected by attenuation, distortion, interference, and noise, that hampers the ability of the receiver to correctly receive the transmitted message signal. Thus error detection and correction methods are implemented to mitigate these effects. Convolution encoder is one such channel encoding technique used at transmitter end for deep space and wireless communication whereas at receiver end the Viterbi decoder decodes the encoded data. Viterbi algorithm is based on principles of maximum likelihood where the optimal trellis path is identified that is followed at the encoder using cumulative hamming distance. This paper presents an SoC based Hardware-Software codesign approach of implementing the Viterbi Decoder along with the entire communication system comperising of random binary pattern generator, convolution encoder, QPSK modulator, QPSK demodulator and quantizer built on a Zynq-7000 All Programmable SoC chip. The blocks are designed using Verilog HDL (Hardware Description Language) using the tools Vivado IDE (Integrated Development Environment) 2017.4 by Xilinx and HDL coder toolbox of MATLAB 2018 $a$ by MathWorks. Simulink model of the communication chain is implemented to simulate the design considering the effect of AWGN (Additive White Gaussian Noise) through the channel and then the partial design is translated to be implemented on a Zynq-7000 AP SoC. This design can find potential applications in Satellite communication, SDR (Software Defined Radio).

In 1995, Best etal. published a formula for the exact bit error probability for Viterbi decoding of the rate R =1/2, memory m = 1 (two-state) convolutional encoder with generator matrix G(D) = (1 1 + D) when used to communicate over the binary symmetric channel. Their formula was later extended to the rate R = 1/2, memory m = 2 (four-state) convolutional encoder with generator matrix G(D) = (1 + D2 1 + D + D2) by Lentmaier et al. In this paper, a different approach to derive the exact bit error probability is described. A general recurrent matrix equation, connecting the average information weight at the current and previous states of a trellis section of the Viterbi decoder, is derived and solved. The general solution of this matrix equation yields a closed-form expression for the exact bit error probability. As special cases, the expressions obtained by Best et al. for the two-state encoder and by Lentmaier et al. for a four-state encoder are used. The closed-form expression derived in this paper is evaluated for various realizations of encoders, including rate R = 1/2 and R = 2/3 encoders, of as many as 16 states. Moreover, it is shown that it is straightforward to extend the approach to communication over the quantized additive white Gaussian noise channel.

Systolic tree structure is a reconfigurable architecture in Field-programmable gate arrays (FPGA) which provide performance advantages. It is used for frequent pattern mining operations. High throughput and cost effective performance are the highlights of the systolic tree based reconfigurable architecture. Frequent pattern mining algorithms are used to find frequently occurring item sets in databases. However, space and computational time requirements are very high in frequent pattern mining algorithms. In the proposed system, systolic tree based hardware mechanism is employed with Weighted Association Rule Mining (WARM) for frequent item set extraction process of the Web access logs. Weighted rule mining is to mine the items which are assigned with weights based on user’s interest and the importance of the items. In the proposed system, weights are assigned automatically to Web pages that are visited by the users. Hence, systolic tree based rule mining scheme is enhanced for WARM process, which fetches the frequently accessed Web pages with weight values. The dynamic Web page weight assignment scheme uses the page request count and span time values. The proposed system improves the weight estimation process with span time, request count and access sequence details. The user interest based page weight is used to extract the frequent item sets. The proposed system will also improve the mining efficiency on sparse patterns. The goal is to drive the mining focus to those significant relationships involving items with significant weights.