Optimal channel code parameter selection for hardware efficient OFDM systems

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost is examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/s constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

The authors propose a novel control channel quality improvement scheme for satellite communication systems using a majority decision method over convolutional coding and Viterbi decoding channels. To improve majority decision performance, which is degraded by burst errors due to Viterbi decoding in conventional serial transmission methods, a parallel transmission method is proposed. The performance of the parallel and serial transmission methods has been analyzed, and experimenta have been carried out using rate 1/2 convolutional encoding and Viterbi decoding (constraint length 4 and 7). It is shown that the parallel transmission method has about 10/sup 10/ times lower block error performance at P/sub e/=1*10/sup -4/ than the conventional method. >

In this study, Field Programmable Gate Array (FPGA) implementation of Conic Section Function Neural Network (CSFNN) for a classification problem focused on iris plant is presented. This work demonstrates for the first time to our knowledge, the feed-forward computation of CSFNN implementation on FPGA. Using l6-bit floating point arithmetic and the look-up tables (LUTs) for the sigmoid function and the square root function, 83% and 72% of slices and LUTs on Spartan 3-E XC3S1600E are used for the realization of CSFNN with five neurons. The classification results obtained from the FPGA implementation and software simulation show that the accuracy error between two platforms is only 0.1%.

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

This paper presents an approach of model-based design for implementing a digital communication system on a field programmable gate array (FPGA) for a software defined radio (SDR). SDR is a popular prototyping platform for wireless communication systems due to its flexibility and utility. A traditional SDR system performs nearly all computations and signal processing tasks on the host computer, and then sends the waveform to the RF front end. For complex algorithms or high data rate, the host computer becomes the processing bottleneck and FPGA is often employed as a hardware accelerator. This paper demonstrates the procedure of using model-based design for SDR targeted on FPGA hardware. A complete digital communication system, including a transmitter with convolutional encoder and a receiver with Viterbi decoder, is implemented on an FPGA-based SDR platform and validated by over-the-air demonstration. Synchronization algorithms, such as carrier frequency offset, phase offset, and time recovery, are also optimized for hardware efficiency.

This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

In this paper we describe a single-node, double precision Field Programmable Gate Array (FPGA) implementation of the Conjugate Gradient algorithm in the context of Lattice Quantum Chromodynamics. As a benchmark of our proposal we invert numerically the Dirac–Wilson operator on a 4-dimensional grid on three Xilinx hardware solutions: Zynq Ultrascale+ evaluation board, the Alveo U250 accelerator and the largest device available on the market, the VU13P device. In our implementation we separate software/hardware parts in such a way that the entire multiplication by the Dirac operator is performed in hardware, and the rest of the algorithm runs on the host. We find out that the FPGA implementation can offer a performance comparable with that obtained using current CPU or Intel’s many core Xeon Phi accelerators. A possible multiple node FPGA-based system is discussed and we argue that power-efficient High Performance Computing (HPC) systems can be implemented using FPGA devices only.

Field Programmable Gate Array (FPGA) has been widely adopted as modern reconfigurable computing platforms. Traditionally, the storage elements in FPGAs are static RAM (SRAM), which has large leakage power and limited scalability. Recently, non-volatile memory (NVM) is proposed to replace the SRAM in FPGA systems for static power and density considerations, at the cost of inducing larger dynamic power. Hybrid FPGAs combine the advantages of SRAM and NVM by employing both SRAM and NVM as logic storage elements. Although the feasibility of hybrid FPGA has been confirmed, the design flow has not fully explored the hybrid features yet, resulting in inferior system performance. Besides, traditional design flow does not consider the reconfiguration cost, which may prolong the reconfiguration procedures and thus degrade the system performance in dynamically reconfigurable FPGA systems. This work proposes a runtime and reconfiguration dual aware placement strategy for dynamically reconfigurable hybrid architecture. The proposed scheme considers the tradeoff between runtime and dynamic reconfiguration latency and optimizes the overall performance of the reconfigurable system. Evaluation shows that the proposed scheme improves the system performance by 14.6% for SRAM-MRAM hybrid FPGAs compared with the default placement strategy.

In this paper we assess the independence of the optimization of source and channel coding parameters. We propose a method to separate the source and channel coding optimization as much as possible while maintaining the possibility of joint optimization. We theoretically derive key parameters that must be passed through an interface between source and channel coding. This separation greatly reduces the complexity of the optimization problem and enhances the flexibility.

This paper presents a hardware implementation of multilayer feedforward neural networks (NN) using reconfigurable field-programmable gate arrays (FPGAs). Despite improvements in FPGA densities, the numerous multipliers in an NN limit the size of the network that can be implemented using a single FPGA, thus making NN applications not viable commercially. The proposed implementation is aimed at reducing resource requirement, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The sequential processing of the layers in an NN has been exploited in this paper to implement large NNs using a method of layer multiplexing. Instead of realizing a complete network, only the single largest layer is implemented. The same layer behaves as different layers with the help of a control block. The control block ensures proper functioning by assigning the appropriate inputs, weights, biases, and excitation function of the layer that is currently being computed. Multilayer networks have been implemented using Xilinx FPGA "XCV400hq240". The concept used is shown to be very effective in reducing resource requirements at the cost of a moderate overhead on speed. This implementation is proposed to make NN applications viable in terms of cost and speed for online applications. An NN-based flux estimator is implemented in FPGA and the results obtained are presented.

FPGA (Field Programmable Gate Arrays) implementation of an off-line handwritten digit recognition system based on elastic meshing directional feature extraction and integrated neural network classifier is proposed in this paper. Elastic meshing directional feature extraction is used to extract the feature of normalized 32*16 handwritten digit images. Integrated neural network classifier with BP (back-propagation) learning algorithm is designed as classifier. The pipeline technology and multi-buffer technology are used in the FPGA implementation of elastic meshing directional feature extraction. FPGA implementation architecture of neural network computing unit and integrated neural network classifier is proposed in this paper. Experiment shows that compared with software-based implementation, FPGA-based system can greatly speed up off-line handwritten digit recognition and is suitable for application in some real-time situations where high process speed and portability are required.

Characterisation of the standard deviation of a time‐series signal has uncommon, yet widespread applications. The usual requirement for a representation of signal standard deviation in real‐time implies a high computation speed. A method based on a field programmable gate array (FPGA) implementation is presented. The technique is benchmarked against conventional computational approaches and shows a single windowed standard deviation update calculation of a 16 bit sample can be achieved in 11 ns on a modern CPU. The FPGA implementation is found to be superior to all other approaches examined with an operation time of below 10 ns, and thus provides a useful tool for the real‐time measurement of the standard deviation of signals above 100 MHz.

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre‐computation (PC) technique to perform multiplication over for trinomials. Consequently, an m ‐bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves ∼28 and 17% improvement in hardware and area‐delay product, respectively, for m = 233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area‐delay, and power‐delay products when compared with similar multipliers available in the literature.