Viterbi Decoding for Satellite and Space Communication

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

The authors propose a novel control channel quality improvement scheme for satellite communication systems using a majority decision method over convolutional coding and Viterbi decoding channels. To improve majority decision performance, which is degraded by burst errors due to Viterbi decoding in conventional serial transmission methods, a parallel transmission method is proposed. The performance of the parallel and serial transmission methods has been analyzed, and experimenta have been carried out using rate 1/2 convolutional encoding and Viterbi decoding (constraint length 4 and 7). It is shown that the parallel transmission method has about 10/sup 10/ times lower block error performance at P/sub e/=1*10/sup -4/ than the conventional method. >

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

This paper presents new computationally efficient and accurate techniques for estimating the performance of specific high-rate punctured convolutional codes and uses these techniques to evaluate the performance of sequential and Viterbi decoders for the best known codes. In particular, it demonstrates that the disparity between sequential and Viterbi decoding increases dramatically for long memory codes with high rates and for such codes, the union bound cannot be used as a criterion for selecting good codes for sequential decoders. In contrast, it shows that the proposed methods can be used as efficient tools for performance evaluation and/or identification of good high-rate punctured convolutional codes for use with sequential decoders.

An efficient and hardware economic channel coding technique is essential in high-speed mobile communication systems. The channel coding parameters will have a large impact on the system performance (data rate and bit error rate) and also on the hardware development in terms of area consumption and timing behaviour. Therefore, important system parameters like code rate, constraint length and Viterbi decoding strategy (single state or best state and the resulting truncation depth for both strategies) have to be decided early in the design flow. The objective of this paper is to discuss the technical tradeoff (system performance and hardware cost) when choosing the channel coding parameters for a system with convolutional encoding and Viterbi decoding. For a wide range of possible channel coding parameters the impact on the system performance and on hardware consumptions, which have been acquired from field programmable gate array (FPGA) implementations, are discussed and compared.

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

Dynamic partial reconfigurable Viterbi decoder for wireless standards

We introduce the notion of innovations for Viterbi decoding of convolutional codes. First, we define a kind of innovation corresponding to the received data, i.e., the input to a Viterbi decoder. Then, the structure of a scarce-state-transition (SST) Viterbi decoder is derived in a natural manner. It is shown that the newly defined innovation is just the input to the main decoder in an SST Viterbi decoder and generates the same syndrome as the original received data does. A similar result holds for quick-look-in codes as well. In this case, however, the precise innovation is not defined. We see that this innovation-like quantity is related to the linear smoothed estimate of the information. The essence of innovations approach to a linear filtering problem is first to whiten the observed data, and then to treat the resulting simpler white-noise observations problem. In our case, this corresponds to the reduction of decoding complexity in the main decoder in an SST Viterbi decoder. We show that the distributions related to the main decoder (i.e., the input distribution and the state distribution in the code trellis for the main decoder) are much biased under moderately noisy conditions. We see that these biased distributions actually lead to the complexity reduction in the main decoder. Furthermore, it is shown that the proposed innovations approach can be extended to maximum-likelihood decoding of block codes as well.

A runtime reconfigurable architecture for high speed Viterbi and turbo decoding is designed and implemented on an FPGA. The architecture can be reconfigured to decode a range of convolutionally coded data with constraint lengths varying from 3 to 9, rates 1/2 and 1/3, and various generator polynomials. It can also be reconfigured to decode turbo coded data with constraint length 4 and rate 1/3. Reconfiguration of the architecture requires a single clock cycle and does not require FPGA reprogramming. The proposed architecture can deliver data rates up to 60.5 Mbit/s for Viterbi decoding and 3.54 Mbit/s for turbo decoding, making it suitable for a range of wireless communication standards like IEEE 802.11a, 3GPP, GSM, GPRS, and many others.

While turbo coding techniques have received much recent attention for their extraordinary coding gains, these techniques inherently suffer latency limitations unacceptable in most telephony applications. Long constraint length (LCL) Viterbi decoding (VD) techniques hold promise for significant coding gains at low latencies. This paper presents two novel architectures for the add-compare-select unit of an LCL VD. The derived bit-serial circuits are shown to be more efficient than traditional bit-serial methods with one solution 24% more efficient than traditional approaches and requiring only 1/2 the I/O. Using these techniques, a hardware Viterbi decoder was designed, built, and tested.

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

A variable-rate soft decision sequential decoder LSI is described in detail. The decoder is more reliable and less expensive than a conventional Viterbi decoder, and thus can more effectively improve the performance of a very small aperture terminal. In implementing the decoder, the authors propose a metric replacing technique and a bit-serial decoding scheme. The former achieves quick restarting after a buffer overflow, replacing the metric of some parity bits with a predefined constant. The latter furnishes rate variability to the decoder, decoding a rate k/n code as a 1/1 code. Besides simplifying the implementation, it reduces the computational effort. With these and other techniques, the authors have succeeded in implementing the decoder on a CMOS gate array of 15 K usable gates. The decoder can be operated at any data rate up to 2 Mb/s. The code rate can be selected from among 1/2, 3/4, and 7/8. For R=1/2 code the decoder achieves 6.5 dB coding gain, which is superior to a K=7 Viterbi decoder by 1.0 dB at 10/sup -6/ output bit error rate and a 64 kb/s data rate. For R=3/4 and 7/8, the decoder exhibits significant superiority to the viterbi decoder at any data rate. >

Maximum likelihood decoding of convolutional codes by Viterbi decoding method is an effective error correcting technique. However, little study on Viterbi decoding of high rate codes has been done since the number of paths entering each trellis state increases as the code rate increases. This paper presents a new maximum likelihood decoding of convolutional codes of rate (n ‐ 1)/n using a trellis. the trellis is drawn according to the state transitions of the syndrome former of the code, and has only one or two paths entering each state rather than 2n‐1 paths as in the case of conventional trellises. Thus, we can replace the 2n‐1‐ary comparisons at each state needed in the conventional Viterbi decoding for the code of rate (n ‐ 1)/n by binary comparisons. the implementation of maximum likelihood decoders for high rate convolutional codes is simplified greatly by this approach. Moreover, this decoding method shows the same performance as that of conventional Viterbi decoding method from the viewpoint of selecting the maximum likelihood code sequence.

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.