Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost is examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/s constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

The authors propose a novel control channel quality improvement scheme for satellite communication systems using a majority decision method over convolutional coding and Viterbi decoding channels. To improve majority decision performance, which is degraded by burst errors due to Viterbi decoding in conventional serial transmission methods, a parallel transmission method is proposed. The performance of the parallel and serial transmission methods has been analyzed, and experimenta have been carried out using rate 1/2 convolutional encoding and Viterbi decoding (constraint length 4 and 7). It is shown that the parallel transmission method has about 10/sup 10/ times lower block error performance at P/sub e/=1*10/sup -4/ than the conventional method. >

A runtime reconfigurable architecture for high speed Viterbi and turbo decoding is designed and implemented on an FPGA. The architecture can be reconfigured to decode a range of convolutionally coded data with constraint lengths varying from 3 to 9, rates 1/2 and 1/3, and various generator polynomials. It can also be reconfigured to decode turbo coded data with constraint length 4 and rate 1/3. Reconfiguration of the architecture requires a single clock cycle and does not require FPGA reprogramming. The proposed architecture can deliver data rates up to 60.5 Mbit/s for Viterbi decoding and 3.54 Mbit/s for turbo decoding, making it suitable for a range of wireless communication standards like IEEE 802.11a, 3GPP, GSM, GPRS, and many others.

In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6 K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5 mW at 100 MHz.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

An efficient and hardware economic channel coding technique is essential in high-speed mobile communication systems. The channel coding parameters will have a large impact on the system performance (data rate and bit error rate) and also on the hardware development in terms of area consumption and timing behaviour. Therefore, important system parameters like code rate, constraint length and Viterbi decoding strategy (single state or best state and the resulting truncation depth for both strategies) have to be decided early in the design flow. The objective of this paper is to discuss the technical tradeoff (system performance and hardware cost) when choosing the channel coding parameters for a system with convolutional encoding and Viterbi decoding. For a wide range of possible channel coding parameters the impact on the system performance and on hardware consumptions, which have been acquired from field programmable gate array (FPGA) implementations, are discussed and compared.

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

Dynamic partial reconfigurable Viterbi decoder for wireless standards

Software-defined radio (SDR) is a challenging domain for language designers. To be useful in the real world, radio protocol implementations must operate at high data rates with low latency, yet to be useful to implementers, a language should allow programmers to express algorithms at a high level of abstraction without having to worry about the very low-level details that are necessary for meeting performance requirements. Ziria demonstrated that a high-level language for writing wireless physical layer (PHY) protocols could be competitive with hand-written C++, but only in a context where performance-critical computations, such as FFT and Viterbi, were still written in C++ and accessed via a foreign function interface. We demonstrate that a new implementation of Ziria, embodied in the kzc compiler, allows even performance-critical blocks such as FFT and Viterbi to be written in a high-level language without sacrificing performance. Because kzc performs whole-program optimization, a radio protocol pipeline using an implementation of Viterbi written in Ziria can outperform an implementation that calls out to . The contributions of this paper fall into two categories. First, we describe two new optimizations in kzc, both of which are critical for wringing performance out of high-level code: an aggressive partial evaluator for Ziria programs, and an automatic lookup-table (LUT) generator. Second, we show how these optimizations allow the efficient implementation of three performance-critical blocks in Ziria: Viterbi decoding, the Fast Fourier Transform (FFT), and the inverse Fast Fourier Transform (IFFT).

In the modern, information driven society managing and handling data is unavoidable. The most common form of data handling is to organize data into tables and complete operations on them in spreadsheets. Sprego (Spreadsheet Lego) is a programming-oriented methodology focusing on schemata construction and authentic problem-solving working with only a limited number of general-purpose functions. In our current study the goal is to present Sprego as an alternative method for spreadsheeting, and to measure its effectiveness in education compared to the traditional surface approach methods. We also aim to highlight the advantages of teaching datamanagement, spreadsheeting, and introduction to programming by applying an algorithmic and schemata centric method in a user-friendly interface. The teaching and testing were carried out in three classes of a local middle and high school with two experimental and one control groups. Based on our results, it is found that the Sprego methodology is significantly more effective than the traditional surface approach methods. Furthermore, it is also proved, in accordance with similar studies in sciences, that students, who had studied traditional spreadsheet management in advance to this experience, have difficulties switching to Sprego. Although these students alternate between the two approaches, our measurements clearly prove that the traditional approach is pushed into the background, as students prefer to solve problems using Sprego. Our findings also imply that traditional methods do not develop long-lasting knowledge which students could rely on, and have a negative effect on their development, while Sprego seems much more reliable.

In cases where the parameters of a forward error correcting encoder (the constraint length K and the generator polynomials) are unknown, they must be obtained before the message data can be recovered. The synthetic impulse response sequence (SIRS) algorithm, through observation and manipulation of the encoded output, composes a synthetic impulse response and from this sequence performs encoder parameter recovery. With these parameters in hand, selection of a suitable (Viterbi) decoder and recovery of message data is straightforward. We apply the SIRS algorithm in a noisy environment. The elements of the algorithm are extended to accommodate erroneous encoded data, and the impact of noise upon the probability of a correct solution are considered.

Use of the Viterbi decoder to decode the (63, 57) Hamming code is considered, Implementation and performance of systematic and nonsystematic codes are addressed. It is shown that a Viterbi decoder for the constraint length seven, rate- 1/2 convolutional code can be used to decode both systematic and nonsystematic (63, 57) Hamming codes, but an additional step is needed to complete the decoding of the systematic code. Bounds and simulation results for postdecoding bit-error probability are given and it is shown that the systematic code performs 0.4 dB better than the nonsystematic code. A heuristic explanation is provided.

Consideration is given to the bit error probability performance of rate 1/2 convolutional codes in conjunction with quaternary phase shift keying (QPSK) modulation and maximum-likelihood Viterbi decoding on fully interleaved Rician fading channels. Applying the generating function union bounding approach, an asymptotically tight analytic upper bound on the bit error probability performance is developed under the assumption of using the Viterbi decoder with perfect fading amplitude measurement. Bit error probability performance of constraint length K=3-7 codes with QPSK is numerically evaluated using the developed bound. Tightness of the bound is examined by means of computer simulation. The influence of perfect amplitude measurement on the performance of the Viterbi decoder is observed. A performance comparison with rate 1/2 codes with binary phase shift keying (BPSK) is provided. >