Development of variable-rate sequential decoder LSI

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost is examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/s constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

An efficient and hardware economic channel coding technique is essential in high-speed mobile communication systems. The channel coding parameters will have a large impact on the system performance (data rate and bit error rate) and also on the hardware development in terms of area consumption and timing behaviour. Therefore, important system parameters like code rate, constraint length and Viterbi decoding strategy (single state or best state and the resulting truncation depth for both strategies) have to be decided early in the design flow. The objective of this paper is to discuss the technical tradeoff (system performance and hardware cost) when choosing the channel coding parameters for a system with convolutional encoding and Viterbi decoding. For a wide range of possible channel coding parameters the impact on the system performance and on hardware consumptions, which have been acquired from field programmable gate array (FPGA) implementations, are discussed and compared.

The increasing demand for high-density and high-speed digital optical recording systems has made the development of advanced coding and signal processing techniques for fast and reliable data recovery increasingly important. In recent years, the parity-check (PC)-code-based reception technique has been widely studied for magnetic recording systems, and it is projected to be highly promising for high-density optical recording. The PC code is an inner error correction code (ECC), which can detect dominant short error events of the system, using only a few parity bits. This reduces the loss in error correction capability of the outer ECC due to random short errors and results in a simple and efficient solution to improve the overall performance. This thesis is dedicated to the design and analysis of PCcode- based recording systems to achieve higher recording capacity with low implementation complexity, for high-density blue laser disc systems. In particular, most of the key components of the PC-code-based optical recording system have been designed and optimized for different recording densities, and different proportions of white noise and media noise. During the development of advanced coding and detection techniques, it becomes necessary to investigate the system’s performance with different coding schemes and recording densities. In Chapter 2 of the thesis, we propose a generalized Braat-Hopkins model for optical recording channels, which provides a fair basis for the performance comparison of detection schemes over different coding schemes and recording densities, for channels with additive, white Gaussian noise (AWGN) and media noise. Various basic issues associated with the PC-code-based systems are investigated in Chapter 3. These include bounds for bit error rates and error event probabilities, the dominant error events at channel detector output, different PC codes, simple and efficient post-processors, the impact of error events that are split across data block boundaries and the corresponding remedy, as well as the effects of code rates and recording densities. Simulation results show that a 4-bit PC code achieves the best performance. The corresponding bit error rates (BERs) are very close to the performance bounds, at both nominal and high densities. Constrained codes, which serve as a key component in the read-write channel of data storage systems, are desired to have a high code rate with low-complexity encoder/decoder. In Chapter 4, we investigate the design of certain capacity-approaching constrained codes for optical recording systems. In particular, we derive analytically the relationship between the number of encoder states and the maximum size of these codes. We identify the minimum number of encoder states that maximizes the code rate, for any desired codeword length. The design of constrained PC codes is key to the development of PCcode- based systems, and the systematic design of efficient constrained PC codes remains a challenging problem. In Chapter 5, we propose a general and systematic code design technique for constructing capacity-approaching constrained PC codes, which can detect any type of error events of the system, with the minimum code rate loss. Compared to the rate 2/3 code without parity, the newly designed constrained 4-bit PC code achieves a performance gain of 2 dB at nominal density, and 1.5 dB at high density, at BER = 10-5. As the dominant noise for high-density optical recording systems, media noise severely degrades the performance of channel detectors and postprocessors that are designed for AWGN. In Chapter 6, we propose two novel modifications to the bit detector to combat media noise. We further develop a data-dependent post-processing scheme for error correction. Compared to the system designed without considering media noise and without PC codes, the overall performance gain of the developed scheme can be more than 11 dB at high media noise levels. In data storage systems, the ECC failure rate (EFR) serves as the ultimate measure of the data recovery performance. In Chapter 7, we develop semi-analytical approaches for estimating the EFR, and analyze EFRs for the developed PC-code-based systems, for the cases without and with interleaving. Our analysis shows that with the optimum interleaving degrees, compared to the rate 9/13 code without parity, the 2-bit PC code achieves a gain of around 0.5 dB, and the 4-bit PC code gains 0.6 dB, at high record ing density and EFR = 10-16. The thesis concludes in Chapter 8 with some suggestions for further work.

Advanced technology was needed for this within the cap of bandwidth, due to new developments in wireless networking and the increasing requirement of high data levels by consumers. One of the promising solutions is a system with 60 GHz Ultra-Wideband (UWB) that supports a data rate of up to 7 Gbps, considered 10 times faster than the Wi-Fi 802.11n data rate. The system uses advanced modulation modulations and coding systems called adaptive modulation and coding (AMC). However, inappropriate modulation level selection and coding rate can lead, in the event of radio frequency interference and a multi-way decline, to a low data rate. In fact, if non-optimum decoder due to the code’s restriction duration was chosen, more output loss occurs. In this paper, we will present explain about the OFDM technology. Also, we will discuss 60 GHZ Frequency Band and all their advantage. So, we will explain the OFDM-UWB systems and convolutional coding and viterbi decoding.

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

In this letter, the error-rate (ER) performance of multiple input and multiple output multi-carrier code-division-multiple-access (MIMO MC-CDMA) is evaluated with the aid of cognitive radio network (CRN). MIMO is proven to be useful for high data rate application. MC-CDMA is used to accommodate higher number of user by eliminating channel impairments. CRN is suggested for 5G network to offer higher bandwidth by exposing idle spectrum. Multi-carrier modulation is processed inverse fast-Fourier transform at transmitter and demodulation at each receiver using fast-Fourier transform. Multi-carrier technique is introduced to obtain bandwidth efficiency and overcome the problem of frequency selectivity. At each mobile station, we estimate user’s information using MMSE based iterative algorithm. Further; the system performance is tested using channel encoder. We structure channel encoder using turbo code which is designed with the help of two convolutional encoder. The input information is interleaved using random interleaver and is fed to second convolutional encoder. We create puncturing matrix using input information and output of two convolutional encoders. Then we puncture parity bit information to obtain necessary code rate. Further, we decode and estimate information using iterative decoder which ensure higher performance with lower signal-to-noise ratio. It is vindicated from simulations that CRN based MIMO MC-CDMA system with iterative decoder swell better ER while ensuring higher data rate for downlink signal transmission.

The emerging trends of wireless communication and ever growing demand of very high data rate from users created the need for new technologies that could satisfy this need under limited bandwidth. A 60-GHz Ultra-Wideband (UWB) system that can support up to 7 Gbps data rate, which is 10 times faster than the data rate of the Wi-Fi 802.11n, is one of the promising options. The system utilizes higher order modulation and advanced coding schemes known as Adaptive Modulation and Coding (AMC). However, inappropriate selection of modulation level and coding rate can lead to low data rate particularly in the presence of Radio Frequency interference and multipath fading. Moreover, further performance degradation occurs when non-optimal decoder due to code constraint length was selected. This paper proposes and evaluates a duplex 60-GHz UWB system employing Orthogonal Frequency Division Multiplexing (OFDM-UWB) to boost the data rate and extend the coverage. Firstly, an OFDM-UWB system employing high order modulation that transmits data simultaneously over multiple carriers spaced apart at precise frequencies been simulated and validated using Matlab. Secondly, the system performance been analyzed when convolutional coding been introduced in term of Bit Error Rate (BER). The simulation results show that the BER performance of 16QAM is worse, with 6 dB penalties at BER of 10−3, compared with that of QPSK. Moreover, simulation also shows that there are 2 dB difference between the performance of R=1/2 and R=7/8, while the highest throughput been achieved when the 3/4 code rate is employed.

MultiBand OFDM (MB-OFDM) UWB [1] is a promising short-range wireless technology for high data rate communications up to 480 Mbps. The UWB receiver uses a Viterbi decoder that must support the highest data rate of 480 Mbps. To achieve such high data rates a sliding block Viterbi decoder is a good design candidate. In this paper, we analyze the tradeoffs involved in the design of sliding block Viterbi decoders for the highest data rates of MB-OFDM UWB systems. We have designed a configurable transmitter/receiver of an MB-OFDM UWB system and an AWGN generator in VHDL and determined the bit error rates of the system running in FPGA. The results indicate the relation between bit error rates and different configuration parameters of the sliding block Viterbi decoder.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

Machine Type Communication (MTC) is becoming an integral part of the Long Term Evolution — Advanced (LTE-A) cellular network. Challenges arise when some of the MTC devices, due to the nature of their applications, are deployed in low signal locations. As per 3GPP requirements, there is a need for additional coverage enhancement up to 20 dB in comparison with LTE category 1 UE for MTC devices. In the previous works reported till now, Repetition Coding is proposed as an effective technique to achieve the required coverage enhancements at cost of longer decoding time. In low signal conditions where many repetitions are required to build the SNR needed, the decoding delay may be unacceptable. For a LTE-A MTC UE, Physical Broadcast CHannel (PBCH) decoding has a very important role and fast, efficient decoding of PBCH will help to improve the device performance. In this paper, we propose to use well established technique called Reduced Search (RS) Viterbi to improve PBCH decoding performance without compromising the time-to-decode. RS Viterbi technique utilizes a priori knowledge of transmitted bits to reduce the size and complexity of trellis, which in turn also reduces probability of choosing incorrect path, i.e., error. Up to 2.2 dB SNR gain is seen in simulation using the RS Viterbi decoding against the conventional Viterbi decoding, which will contribute in improving the sensitivity of MTC devices for better reachability.

This paper relates to the application method of channel state information (CSI) to the Viterbi (maximum likelihood) decoder in the digital terrestrial television broadcasting system. The proposed Viterbi decoder uses the CSI derived from the pilots inserted in the transmitter of the COFDM (coded orthogonal frequency division multiplexing) system. The CSI is calculated by interpolation using the pilots in the receiver. The active real (I) and imaginary (Q) data after equalization are transferred to the branch metric calculation block that decides the euclidean distance for soft decision decoding and also the estimated CSI values are transferred to the same block. After calculating the euclidean distance for the soft decision decoding, the euclidean distance of the branch metric is multiplied by CSI. To do so, new branch metric values that consider each carrier state information are obtained. We simulated this method in Rayleigh fading defined in the ETSI standard. From the simulation, this method has better performance of about 0.15 dB to 0.7 dB and 2.2 dB to 2.9 dB in the Rayleigh channel than that of conventional soft decision Viterbi decoding with or without a bit interleaver where the constellation is QPSK, l6-QAM and 64-QAM.

The authors present a low-complexity convolutional decoding scheme the error selective Viterbi decoder (ESVD) which improves the trellis code search of a conventional Viterbi decoder (VD). Use of the ESVD leads to a significant computational savings under typical channel conditions owing to the isolation of erroneous data stretches and the decoding (only) of the error sequence through a simplified VD search. The effectiveness of multi-bit ESVD schemes is verified for different encoders and data quantisations using Monte Carlo simulations.

Maximum likelihood decoding of convolutional codes by Viterbi decoding method is an effective error correcting technique. However, little study on Viterbi decoding of high rate codes has been done since the number of paths entering each trellis state increases as the code rate increases. This paper presents a new maximum likelihood decoding of convolutional codes of rate (n ‐ 1)/n using a trellis. the trellis is drawn according to the state transitions of the syndrome former of the code, and has only one or two paths entering each state rather than 2n‐1 paths as in the case of conventional trellises. Thus, we can replace the 2n‐1‐ary comparisons at each state needed in the conventional Viterbi decoding for the code of rate (n ‐ 1)/n by binary comparisons. the implementation of maximum likelihood decoders for high rate convolutional codes is simplified greatly by this approach. Moreover, this decoding method shows the same performance as that of conventional Viterbi decoding method from the viewpoint of selecting the maximum likelihood code sequence.