An effective simplifying scheme for Viterbi decoder

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost is examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/s constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

A variable-rate soft decision sequential decoder LSI is described in detail. The decoder is more reliable and less expensive than a conventional Viterbi decoder, and thus can more effectively improve the performance of a very small aperture terminal. In implementing the decoder, the authors propose a metric replacing technique and a bit-serial decoding scheme. The former achieves quick restarting after a buffer overflow, replacing the metric of some parity bits with a predefined constant. The latter furnishes rate variability to the decoder, decoding a rate k/n code as a 1/1 code. Besides simplifying the implementation, it reduces the computational effort. With these and other techniques, the authors have succeeded in implementing the decoder on a CMOS gate array of 15 K usable gates. The decoder can be operated at any data rate up to 2 Mb/s. The code rate can be selected from among 1/2, 3/4, and 7/8. For R=1/2 code the decoder achieves 6.5 dB coding gain, which is superior to a K=7 Viterbi decoder by 1.0 dB at 10/sup -6/ output bit error rate and a 64 kb/s data rate. For R=3/4 and 7/8, the decoder exhibits significant superiority to the viterbi decoder at any data rate. >

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the minimized method (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 /spl mu/ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

This paper relates to the application method of channel state information (CSI) to the Viterbi (maximum likelihood) decoder in the digital terrestrial television broadcasting system. The proposed Viterbi decoder uses the CSI derived from the pilots inserted in the transmitter of the COFDM (coded orthogonal frequency division multiplexing) system. The CSI is calculated by interpolation using the pilots in the receiver. The active real (I) and imaginary (Q) data after equalization are transferred to the branch metric calculation block that decides the euclidean distance for soft decision decoding and also the estimated CSI values are transferred to the same block. After calculating the euclidean distance for the soft decision decoding, the euclidean distance of the branch metric is multiplied by CSI. To do so, new branch metric values that consider each carrier state information are obtained. We simulated this method in Rayleigh fading defined in the ETSI standard. From the simulation, this method has better performance of about 0.15 dB to 0.7 dB and 2.2 dB to 2.9 dB in the Rayleigh channel than that of conventional soft decision Viterbi decoding with or without a bit interleaver where the constellation is QPSK, l6-QAM and 64-QAM.

We introduce the notion of innovations for Viterbi decoding of convolutional codes. First, we define a kind of innovation corresponding to the received data, i.e., the input to a Viterbi decoder. Then, the structure of a scarce-state-transition (SST) Viterbi decoder is derived in a natural manner. It is shown that the newly defined innovation is just the input to the main decoder in an SST Viterbi decoder and generates the same syndrome as the original received data does. A similar result holds for quick-look-in codes as well. In this case, however, the precise innovation is not defined. We see that this innovation-like quantity is related to the linear smoothed estimate of the information. The essence of innovations approach to a linear filtering problem is first to whiten the observed data, and then to treat the resulting simpler white-noise observations problem. In our case, this corresponds to the reduction of decoding complexity in the main decoder in an SST Viterbi decoder. We show that the distributions related to the main decoder (i.e., the input distribution and the state distribution in the code trellis for the main decoder) are much biased under moderately noisy conditions. We see that these biased distributions actually lead to the complexity reduction in the main decoder. Furthermore, it is shown that the proposed innovations approach can be extended to maximum-likelihood decoding of block codes as well.

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.

Machine Type Communication (MTC) is becoming an integral part of the Long Term Evolution — Advanced (LTE-A) cellular network. Challenges arise when some of the MTC devices, due to the nature of their applications, are deployed in low signal locations. As per 3GPP requirements, there is a need for additional coverage enhancement up to 20 dB in comparison with LTE category 1 UE for MTC devices. In the previous works reported till now, Repetition Coding is proposed as an effective technique to achieve the required coverage enhancements at cost of longer decoding time. In low signal conditions where many repetitions are required to build the SNR needed, the decoding delay may be unacceptable. For a LTE-A MTC UE, Physical Broadcast CHannel (PBCH) decoding has a very important role and fast, efficient decoding of PBCH will help to improve the device performance. In this paper, we propose to use well established technique called Reduced Search (RS) Viterbi to improve PBCH decoding performance without compromising the time-to-decode. RS Viterbi technique utilizes a priori knowledge of transmitted bits to reduce the size and complexity of trellis, which in turn also reduces probability of choosing incorrect path, i.e., error. Up to 2.2 dB SNR gain is seen in simulation using the RS Viterbi decoding against the conventional Viterbi decoding, which will contribute in improving the sensitivity of MTC devices for better reachability.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

Maximum likelihood decoding of convolutional codes by Viterbi decoding method is an effective error correcting technique. However, little study on Viterbi decoding of high rate codes has been done since the number of paths entering each trellis state increases as the code rate increases. This paper presents a new maximum likelihood decoding of convolutional codes of rate (n ‐ 1)/n using a trellis. the trellis is drawn according to the state transitions of the syndrome former of the code, and has only one or two paths entering each state rather than 2n‐1 paths as in the case of conventional trellises. Thus, we can replace the 2n‐1‐ary comparisons at each state needed in the conventional Viterbi decoding for the code of rate (n ‐ 1)/n by binary comparisons. the implementation of maximum likelihood decoders for high rate convolutional codes is simplified greatly by this approach. Moreover, this decoding method shows the same performance as that of conventional Viterbi decoding method from the viewpoint of selecting the maximum likelihood code sequence.

Todays need is for increased content and bandwidth to drive communication systems, error control coding has a great demand. To maintain high reliable data and to improve the Bit Error Rate (BER), error correction technique like the Viterbi algorithm is one of the promising solutions. Though it is useful for error correction it dissipates large power. A lot many researches were carried out at architectural as well as algorithmic level to optimize the ACS (Add compare and Select) unit and Survival Memory Management in Synchronous Viterbi Decoders. But still there is a problem of power dissipation which requires more technical solutions. Due to requirements of high speed, low power, low weight and long battery life a low power Viterbi decoders has a great demand in the communication field. This paper proposed the method for survivor path storage and decoding as Minimum Transition Hybrid Register Exchange Method along with handshaking protocol as Level Encoded dual rail (LEDR) encoding to make the system asynchronous. The whole system has been designed on algorithmic level and Simulation is done on Xilinx Tool for Asynchronous Viterbi Decoder using MTHREM.

When estimating the bit error rate (BER) of communications systems using Monte Carlo (MC) simulation, importance sampling (IS) may be a powerful method for reducing simulation runtimes. The paper presents an IS technique combined with error event simulation in order to evaluate efficiently the performance of Viterbi decoding used with a binary nonsymmetric channel and with a binary erasure channel. Two biasing approaches are employed, stationary and nonstationary models. Comparative results between the two models and traditional MC methods are presented.

This study investigates the constellation mapping of the 3-bit soft-decision Viterbi decoder and the decoding system of the Viterbi decoder for trellis-coded modulation (TCM) decoding. By referring to the IESS-310 TCM standard coding scheme, LabVIEW FPGA is employed to design the corresponding decoding circuits of the 3-bit soft-decision TCM Viterbi decoder in a software-defined radio (SDR) system [1]. Finally, the study employs TCM coding and decoding circuits designed by using LabVIEW FPGA to simulate the error rate curve in the AWGN channel. The simulation results surpass the bit error rate (BER) curves of QPSK and 8PSK and the IESS-310 standard.

Significant power reduction can be achieved by exploiting real-time variation in system characteristics. An approach is proposed and studied herein that exploits variation in signal transmission system characteristics to reduce power consumption while decoding convolutional codes. With this approach, Viterbi decoding is adaptively approximated by varying the pruning threshold of the T-algorithm and truncation length while employing trace-back memory management. A heuristic is given for finding and adaptively applying pairs of pruning threshold and truncation length values that significantly reduce power to variations in signal-to-noise ratio (SNR), code rate, and maximum acceptable bit-error rate (BER). The power reduction potential of different levels of adaptation is studied. High-level energy reduction estimates of 80% to 97% compared with Viterbi decoding are shown. Implementation insight and general conclusions about when applications can particularly benefit from this approach are given.

Since 1967, Viterbi decoder is considered to be the maximum-likelihood decoding algorithm for convolutional codes and codes with state machine representation. Distance-preserving mapping codes designed from the mapping of convolutional codes outputs to permutation sequences make use of constructions that help choosing the best mapping and improving the performance of Viterbi decoding by improving the distances metrics in the trellis diagram of the code. Combining these new designed codes with M-FSK modulation is to combat permanent frequency disturbances in power-line communications channel. The choice of the M-FSK detector also plays a role in the improvement of the decoding process at the demodulator. Viterbi's ratio Threshold test (VRTT) is modified to avoid the erasure detection, as we are not interested in such errors in our channel and to be considered as a soft decision detection for the envelope detector.