Power-efficient decoder implementation based on state transparent convolutional codes

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost is examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/s constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

Low-power microarchitecture designs of Viterbi decoder are considered one of the on-demanding issues in Very Large-Scale Integration (VLSI). Viterbi decoders consume 35% of the power and 76% of the complexity in digital communication schemes, e.g., IEEE 802.11 a/g WLAN schemes. Development of Viterbi decoder itself reduces dramatically system complexity; the decoder has a source of power sink unit which rises in Add Compare-Select (ACS) unit. Various levels of development exist in VLSI such as architecture, microarchitecture, circuit, and transistor. ACS is structured of adder, comparator, and selector, so microarchitecture development of ACS unit intends one of these superior blocks. Adders in VLSI designs have a tremendous interest as they are the kernel of any digital system so enhancing this basic building block, which is used over and over, influences system specification. This paper targets different microarchitectural approaches to shrink the power of this unit which enhances overall system specification. Microarchitecture development encompasses using another block instead of the existing one or repositioning current blocks. In this review paper, comparisons of different parallel adders are presented to achieve low consumption power while obtaining high-speed operation of the addition, and an arrangement of ACS blocks to reduce the complexity of the decoder is also provided.

The authors propose a novel control channel quality improvement scheme for satellite communication systems using a majority decision method over convolutional coding and Viterbi decoding channels. To improve majority decision performance, which is degraded by burst errors due to Viterbi decoding in conventional serial transmission methods, a parallel transmission method is proposed. The performance of the parallel and serial transmission methods has been analyzed, and experimenta have been carried out using rate 1/2 convolutional encoding and Viterbi decoding (constraint length 4 and 7). It is shown that the parallel transmission method has about 10/sup 10/ times lower block error performance at P/sub e/=1*10/sup -4/ than the conventional method. >

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.

In this paper we investigate power dissipation for the Viterbi algorithm. We modified the Viterbi algorithm in a power-aware way and employed several low-power techniques to reduce its power dissipation. The first modification is re-arranging of arithmetic operations to reduce the number and complexity of computational components. Another simplification is made in the survivor memory unit by storing only one bit to identify the previous state in the survivor path, and by assigning each register to the decision vector of each clock cycle. This approach eliminates unnecessary shift operations and enables us to apply a clock-gating technique to disable all of the registers but one. The final modification stems from the property of converging all of the trace-back paths at a same state regardless of their initial state. Thus, there is no need to store a global winner path. The schemes employed in our low-power design are precomputation, clock-gating, toggle filtering, and using double edge-triggered flip-flops. The power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of an original Viterbi decoder design by 88%.

A variable-rate soft decision sequential decoder LSI is described in detail. The decoder is more reliable and less expensive than a conventional Viterbi decoder, and thus can more effectively improve the performance of a very small aperture terminal. In implementing the decoder, the authors propose a metric replacing technique and a bit-serial decoding scheme. The former achieves quick restarting after a buffer overflow, replacing the metric of some parity bits with a predefined constant. The latter furnishes rate variability to the decoder, decoding a rate k/n code as a 1/1 code. Besides simplifying the implementation, it reduces the computational effort. With these and other techniques, the authors have succeeded in implementing the decoder on a CMOS gate array of 15 K usable gates. The decoder can be operated at any data rate up to 2 Mb/s. The code rate can be selected from among 1/2, 3/4, and 7/8. For R=1/2 code the decoder achieves 6.5 dB coding gain, which is superior to a K=7 Viterbi decoder by 1.0 dB at 10/sup -6/ output bit error rate and a 64 kb/s data rate. For R=3/4 and 7/8, the decoder exhibits significant superiority to the viterbi decoder at any data rate. >

The authors present a low-complexity convolutional decoding scheme the error selective Viterbi decoder (ESVD) which improves the trellis code search of a conventional Viterbi decoder (VD). Use of the ESVD leads to a significant computational savings under typical channel conditions owing to the isolation of erroneous data stretches and the decoding (only) of the error sequence through a simplified VD search. The effectiveness of multi-bit ESVD schemes is verified for different encoders and data quantisations using Monte Carlo simulations.

An implementation of the Viterbi algorithm (VA) can be divided into three basic units, the transition metric unit, the added-compare-select unit, and the survivor memory unit (SMU). In this paper, a decoding scheme of SMU for a strongly connected Viterbi decoder is presented. In practice, two approaches, viz., the register-exchange method and the trace-back method, are very useful for survivor memory management. The presented decoding scheme has the property which is suitable for VLSI design using the systolic architecture. Finally, the conclusions show that the drawbacks occurring in the conventional SMU coding scheme can be overcome when the trellis is strongly connected instead of the original trellis.

This paper addresses the implementation and performance of hybrid-ARQ error control on a coherent slowly fading Ricean channel. Using a convolutional code with soft-decision Viterbi decoding for error correction, there are two methods for realizing the simultaneous error detection capability which characterizes hybrid-ARQ error control: (1) a two code approach which pre-encodes the information based on a high rate CRC code and performs error detection on the output of the Viterbi decoder, (2) a single code approach which modifies the Viterbi decoder to reject packets with low reliability during the Viterbi decoding process. The resulting analysis shows that the two code method is more robust than single code method with the most significant performance advantages realized for Rayleigh fading. The two code approach provides acceptable error rate performance and offers a throughput characteristic which is not as sensitive to changes in the average SNR as the single code approach. Since the implementational complexity of the two methods is comparable, the two code method is the preferred implementation for hybrid-ARQ on flat fading channels.

The puncturing technique allows obtaining high-rate convolutional codes from low-rate convolutional codes used as mother codes. This technique has been successfully applied to generate good high-rate convolutional codes which are suitable for Viterbi and sequential decoding. In this paper, we investigate the puncturing technique for convolutional self-doubly orthogonal codes (CSO/sup 2/C) which are decoded using an iterative threshold-decoding algorithm. Based on an analysis of iterative threshold decoding of the rate-R=b/(b+1) punctured systematic CSO/sup 2/C, the required properties of the rate-R=1/2 systematic convolutional codes (SCCs) used as mother codes are derived. From this analysis, it is shown that there is no need for the punctured mother codes to respect all the required conditions, in order to maintain the double orthogonality at the second iteration step of the iterative threshold-decoding algorithm. The results of the search for the appropriate rate-R=1/2 SCCs used as mother codes to yield a large number of punctured codes of rates 2/3/spl les/R/spl les/6/7 are presented, and some of their error performances evaluated.

In this paper, the performance comparison of serially concatenated Recursive systematic convolutional (RSC) code system with Non-systematic convolutional (NSC) code system is conduct. The two models of serially concatenated convolutional code is tested over Additive White Gaussian (AWGN) channel, Binary Phase-Shift Keying (BPSK) modulation and Viterbi decoder using MATLAB simulation. In first model of serially concatenated convolutional code uses Recursive systematic convolutional (RSC) as outer and inner encoder. In second model of serially concatenated convolutional code uses Non-systematic convolutional (NSC) as outer and inner encoder. The outer and inner encoders are concatenated with the help of interleaver. For decoding a non-iterative Viterbi decoding scheme is performed with two Viterbi decoder are concatenated by de-interleaver. The MATLAB simulation results shows that the performance of RSC-RSC concatenated code gives the better bit error rate (BER) than the NSC-NSC concatenated code.

Consideration is given to the bit error probability performance of rate 1/2 convolutional codes in conjunction with quaternary phase shift keying (QPSK) modulation and maximum-likelihood Viterbi decoding on fully interleaved Rician fading channels. Applying the generating function union bounding approach, an asymptotically tight analytic upper bound on the bit error probability performance is developed under the assumption of using the Viterbi decoder with perfect fading amplitude measurement. Bit error probability performance of constraint length K=3-7 codes with QPSK is numerically evaluated using the developed bound. Tightness of the bound is examined by means of computer simulation. The influence of perfect amplitude measurement on the performance of the Viterbi decoder is observed. A performance comparison with rate 1/2 codes with binary phase shift keying (BPSK) is provided. >