Design and performance evaluation of a superscalar digital signal processor

Editorial. Design and application of digital signal processors

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMS, and the chip size is 10 mm x 10.1 mm which is fabricated using a 0.8 μm 2 metal CMOS technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32k (2k x 16 bit) RAM, and 240k (10kx24 bit) ROM. The die size is 8.7 mmx8.3 mm and the chip is fabricated using 0.8 μm CMOS technology.

The surge in interest regarding the next generation of optical fiber transmission has stimulated the development of digital signal processing (DSP) schemes that are highly cost-effective with both high performance and low complexity. As benchmarks for nonlinear compensation methods, however, traditional DSP designed with block-by-block modules for linear compensations, could exhibit residual linear effects after compensation, limiting the nonlinear compensation performance. Here we propose a high-efficient design thought for DSP based on the learnable perspectivity, called learnable DSP (LDSP). LDSP reuses the traditional DSP modules, regarding the whole DSP as a deep learning framework and optimizing the DSP parameters adaptively based on backpropagation algorithm from a global scale. This method not only establishes new standards in linear DSP performance but also serves as a critical benchmark for nonlinear DSP designs. In comparison to traditional DSP with hyperparameter optimization, a notable enhancement of approximately 1.21 dB in the Q factor for 400 Gb/s signal after 1600 km fiber transmission is experimentally demonstrated by combining LDSP and perturbation-based nonlinear compensation algorithm. Benefiting from the learnable model, LDSP can learn the best configuration adaptively with low complexity, reducing dependence on initial parameters. The proposed approach implements a symbol-rate DSP with a small bit error rate (BER) cost in exchange for a 48% complexity reduction compared to the conventional 2 samples/symbol processing. We believe that LDSP represents a new and highly efficient paradigm for DSP design, which is poised to attract considerable attention across various domains of optical communications.

Experimental facilities of Nuclear Power Plant (NPP) use simulated nuclear fuel clusters for conducting research studies to understand the effect of power/temperature transients on nuclear fuel. Powering those transients in an experimental facility is performed by electrical heating analogous to nuclear fission heating by controlled high current through high power converters. The desired power/temperature profile can be obtained by controlling the reference current of the phase-controlled converter system regardless of input voltage and load resistance variations. This paper presents design and performance simulation of Digital Signal Processor (DSP) controlled twelve-pulse 24 kA AC- DC thyristorised converter powering nuclear fuel cluster simulators. The target controller is a TI DSP TMS320F28335, for low voltage high current application in close loop system. The thyristor converters are operated individually as well as in parallel for high DC current supply to fuel rod cluster simulator. The performance simulation results highlighting waveforms of various electrical parameters are presented for demonstration of proposed design validation.

Recent advances in the design of digital signal processing (DSP) equipments have broadened the appeal of this technology to satellite customers. Each digital signal processor has up and down converters associated with it in order to interface with the rest of a payload RF subsystem, consequently the need for multi-channel frequency converters that can provide a low cost per channel solution is now of increasing importance. The subject of this paper is the design of such a multi channel down-converter that provides an L band to Baseband frequency conversion, which has typically 100-200 channels. The key factor in achieving the desired low cost per channel is the use of a multi layer, multi RF channel, high temperature cofired ceramic tile. This complex tile incorporates RF tracks as well as DC interconnections and local oscillator signal distribution. The module design presented in this paper uses 13 hybrids per RF channel, thus having 104 hybrids for a fully populated 8 channel down-converter module. This has been designed and developed by EADS Astrium UK as part of the next generation processor (NGP) development jointly funded with ESA.

Architecture design of virtual-optics data security using parallel hardware and software

Polar modulation techniques offer the capability of multimode wireless systems and the potential for a high efficiency power amplifier (PA). This paper describes a new design of digital signal processing (DSP) engine for the polar transmitter. The digital part includes a rectangular-to-polar converter and digital phase modulator, and the engine is designed for the EDGE (2.5G) system. We employ the coordinate rotation digital computer (CORDIC) and direct digital frequency synthesizer (DDFS) techniques in our design. A prototype chip has been designed and fabricated in the UMC 0.18 /spl mu/m CMOS process with 1P6M technology.

In this paper, a control design of Digital Signal Processor based a power factor corrected(PFC) converter and a bidirectional converter for Plug-In Hybrid Electric Vehicles (PHEVs) is discussed. In order to design current and voltage controllers of the PFC converter and the bi-directional converter for PHEVs, small signal models are used. Design procedures of current controllers for the PFC controller and the bi-directional converter are explained and analyzed by using small signal models and bode plots. The suggesting design procedures of controllers for the PFC converter and the bi-directional converter are verified, and validated throughout simulations and a DSP based prototype.

The education of students in the design of DSP (Digital Signal Processor) based systems is achieved through courses including lectures and laboratory sessions. Traditionally, the laboratory sessions take place in the hands-on laboratories and the physical presence of both students and instructors is required. This paper presents the online conduction of the System Design with DSPs postgraduate course's laboratory sessions utilizing the R-DSP Lab (Remote Digital Signal Processors Laboratory). This interactive RL (Remote Laboratory) allows the students to verify their DSP applications which are written by them in C and/or assembly programming language without time and place restrictions. It also supports the remote control of the available laboratory equipment through an internet accessible and user-friendly control environment. However, the most important feature of the R-DSP Lab which is proposed in this paper, is the remote control of student's DSP applications through GUIs (Graphical User Interfaces) developed by them. This feature is demonstrated through an example concerning the implementation and verification processes of a real-time DTMF (Dual Tone Multi Frequency) encoder/decoder. In this example the DSP application is remotely controlled through a LabVIEW based GUI developed by the students following the instructions of the corresponding laboratory session. The assessment and evaluation of both the System Design with DSPs laboratory sessions and the R-DSP Lab are also discussed in this paper.

This paper presents a multiprecision (MP) dynamic and partially reconfigurable fir filter that incorporates variable precision, parallel processing (PP) multiplier, razor-based error detection, dynamic frequency scaling and dedicated operands scheduling to give optimum performance for a variety of operating conditions. Each of the building blocks of the proposed architecture can either work as independent smallerprecision systems or work in parallel to execute higher-precision system. Our aim is to realize a less-delay; area-efficient reconfigurable digital signal processing design that is implemented using Xilinx Synthesis Tool on Virtex5 FPGA kit. The proposed design provides area efficiency and flexibility by permitting dynamically insertion and/or removal of the individual modules to execute various taps for the partial reconfigurable FIR filters. The FIR Filters are being designed using HDL languages since speed is an important interest in this era; the main objective is to improve the speed of the system. In the whole system if the speed of the individual block is improved the overall speed of the system is enhanced. The synthesis results show that the proposed MP design features a minimum-delay and also a reduction in circuit area when compared with reconfigurable fir filter using conventional fixed-width multiplier.

The design of a low-power digital signal processor requires an energy-driven approach to optimize the processing algorithm and hardware architecture over area, time and energy. In addition, the detailed understanding of the interactions between algorithm and architecture is crucial for the overall energy optimized system design and partitioning. To accurately characterize a system, a complete algorithm and architecture need to be simulated together over a representative set of input signals, and the simulator's speed is important. The existing academic and commercial simulation tools lack the ability to efficiently model the energy consumption of a complete system. The authors introduce OPERAS (Object-oriented Power Estimating Restructurable Architecture Simulator), an object-oriented system simulator with power estimation capability. OPERAS's design uses object-oriented principles and efficient C++ language to model and simulate the system behavior.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

We present a new technique to the design and real-time implementation of fuzzy control system basedon digital signal processors in order to improve the precision and robustness for system of industrial robot in this paper. The need to meet demanding control requirement in increasingly complex dynamical control systems under significant uncertainties, leads toward design of intelligent manipulation robots. The TMS320C80 is used in implementing real time fuzzy control to provide an enhanced motion control for robot manipulators. In this paper, a Self-Organizing Fuzzy Controller for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variables of the controller. In the synthesis of a Fuzzy Logic Controller, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult Self-Organizing Fuzzy Controller is proposed for a hierarchical control structure consisting of basic and high levels that modify control rules. The proposed Self-Organizing Fuzzy Controller scheme is simple in structure, fast in computation, and suitable for implementation of real-time control. Performance of the SOFC is illustrated by simulation and experimental results for a Dual-Arm robot with eight joints.

This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.

The aim of this research is the development and analysis of digital signal processing techniques for enhancing performance in coherent optical communication systems. While much of the current digital techniques are identical to those found in the digital wireless literature, we will investigate improvements in performance to be obtained by tailoring modulation and DSP post-processing algorithms to the optical. The combination of polarization-multiplexing and quadrature phase shift-keying (PM-QPSK or DP-QPSK) is emerging as one the most promising solutions to reach bit rates of 100 Gbps and higher. At the receiver end, the use of digital signal processing (DSP) [1, 2] results in significant deployment improvement over the traditional implementation. This application note shows a practical design of a 100 Gbps DP-QPSK transmission system using coherent detection with digital signal processing for distortion compensation.

Objective To investigate and design a coincidence detection system for an all-digital small animal PET scanner and evaluate its preliminary performance properties.Methods This coincidence module adopted a coincidence identification mode based on singles data in list-mode.Using digital signal processing technology,energy calibration,crystal identification,timing alignment and coincidence events extraction were performed on singles data in list-mode.The obtained data could be used for image reconstruction.Results The 13 × 13 crystal array was well recognized by the position histogram of one lutetium yttrium orthosilicate (LYSO) crystal block.In the coincidence timing histogram of the micro-Derenzo phantom,1.36 ns full width at half maximum was obtained.The rods with a diameter of 1.2 mm were clearly displayed in the reconstructed image of the micro-Derenzo phantom.Conclusion The coincidence module can provide satisfactory performance to meet the design needs of an all-digital small animal PET scanner. Key words: Tomography, emission-computed ; Animal ; Software design