Design and verification of real-time systems

Real-time systems are used in many critical applications. Verification of these real-time systems is essential. Presented here is a method for modeling real-time systems and computing the model's timing characteristics automatically. From a data-driven model of the system an equivalent finite state machine representation of the system is produced by this package. To provide efficient traversal of this large state space an ordered binary decision diagram (OBDD) is used to represent the state machine using symbolic methods. Algorithms have been developed to find the largest and smallest distance (times) between any two state sets. From these algorithms schedulability of the real-time system can be determined.

In this paper, we investigate the modeling and verification of real time systems using a case study on transmission protocol, CSMA/CD. Modeling and verification of real time systems is hot research topic which has practical implications. Such systems are considered as mission critical, as its correctness within timed constraints are of great importance. Through modeling and verifying CSMA/CD protocol using timed extension of CSP (TCSP) modeling techniques in PAT, we propose a formal model for CSMA/CD protocol and verify its critical properties like deadlock-freeness, divergence-freeness and collision detection in a given bounded delay. The integrated reduction techniques in PAT help in carrying out the verification with reasonable speed and results.

The specification of reactive and real-time systems must be supported by formal, mathematically-founded methods in order to be satisfactory and reliable. Temporal logics have been used to this end for several years. Temporal logics allow the specification of system behavior in terms of logical formulas, including temporal constraints, events, and the relationships between the two. In the last ten years, temporal logics have reached a high degree of expressiveness. Most of the temporal logics proposed in the last few years can be used for specifying reactive systems, although not all are suitable for specifying real-time systems. In this paper we present a series of criteria for assessing the capabilities of temporal logics for the specification, validation, and verification of real-time systems. Among the criteria are the logic's expressiveness, the logic's order, presence of a metric for time, the type of temporal operators, the fundamental time entity, and the structure of time. We examine a selection of temporal logics proposed in the literature. To make the comparison clearer, a set of typical specifications is identified and used with most of the temporal logics considered, thus presenting the reader with a number of real examples.

The task of checking if a computer system satisfies its timing specifications is extremely important. These systems are often used in critical applications where failure to meet a deadline can have serious or even fatal consequences. This paper presents an efficient method for performing this verification task. In the proposed method a real-time system is modeled by a state-transition graph represented by binary decision diagrams. Efficient symbolic algorithms exhaustively explore the state space to determine whether the system satisfies a given specification. In addition, our approach computes quantitative timing information such as minimum and maximum time delays between given events. These results provide insight into the behavior of the system and assist in the determination of its temporal correctness. The technique evaluates how well the system works or how seriously it fails, as opposed to only whether it works or not. Based on these techniques a verification tool called Verus has been constructed. It has been used in the verification of several industrial real-time systems such as the robotics system described below. This demonstrates that the method proposed is efficient enough to be used in real-world designs. The examples verified show how the information produced can assist in designing more efficient and reliable real-time systems.

An approach to the modeling and verification of real-time systems is presented. The Specification PEARL description language is used for hardware/software modeling. It has its origins in the standard Multiprocessor PEARL language. Its usefulness has been enhanced for asymmetrical multiprocessor system modeling, and parameters for schedulability analysis have been added. It is meant to be an over-layer for PEARL programs and supports the corresponding program model. The detailed program models are represented internally by timed state transition automata. The model of the co-designed system is verified for feasibility with co-simulation. The resulting information may be used for changes in the current design to gain a feasible model of the system. After that, the program models may be enhanced to their full functionality. Schedulability analysis, which should provide the designer with more precise information, can then be done. The new information can be reused on the system model in order to discover bottlenecks or possible discrepancies with the estimated times. By utilising this methodology, the possibility of implementing a non-feasible system should be minimised.

Specification and verification of real-time systems are important research topics with crucial applications; however, the so-called state space explosion problem often prevents model checking to be used in practice for large systems. In this work, we present a self-contained toolkit to analyze real-time systems specified using event-recording automata (ERAs), which supports system modeling, animated simulation, and fully automatic compositional verification based on learning techniques. Experimental results show that our tool outperforms the state-of-the-art timed model checker.

The need of conceiving reliable real-time systems is crucial for the software engineering. This paper is dedicated to the specification and the verification of land transportation systems taken as an application domain. We present a case study in the area of transportation. The system consists of several automated vehicles called CyCab, that have to communicate with a station. The components are modeled with timed automata and some properties are expressed in the timed logic TCTL to be checked by the model checking tool Kronos. These systems, which are both distributed and embedded, require to express non functional-properties, for example a response time constrained.

Areas of computer application are being broadened rapidly due to the rapid improvement of the performance of computer hardware. Applications that were not feasible before are now becoming feasible with high-performance computers. This results in increased demands for computer applications that are large and have complex temporal characteristics. Most analysis methods available, however, cannot handle large, complex real-time systems adequately; They do not scale-up, lack formalism to represent complex features and perform analyses with mathematical rigor, do not support analyses from different viewpoints, or are too hard to learn and apply. TVe need analysis methods that support formal specification and verification of real-time systems. Incremental performance of specification and analysis of systems from different viewpoints (e.g., user, analyst ) must also be supported with languages appropriate for each different viewpoint and for the users involved. This paper introduces a real-time systems analysis method, named PARTS, that aims at providing above features. PARTS supports analyses from two viewpoints: external viewpoint, a view of the sys-Permission tern from the user's perspective, and internal viewpoint, a view from the developer's perspective. These viewpoints are specified using formal languages, which are: Real-Time Events Trace (RTET) for the external viewpoint, and Time Enriched Statecharts (TES) and PARTS Data Flow Diagram (PDFD) for the internal viewpoint. All PARTS languages are based on the Real-Time Temporal Logic (RTTL), and consistency of the specifications made from two different viewpoints are analyzed based on the same RTTL formalism. PARTS converts RTET and TES specifications to RTTL specifications, which are then integrated and analyzed for consistency. All of the PARTS specificaticm languages support the top-down strategy to handle complexity.

Time Petri nets are a powerful formal model for the specification and verification of real-time systems. End-to-end delays in task execution are a key requirement to real-time systems. In this paper, we propose a state class method based on time Petri nets for the computation of end-to-end delays. By introducing time constraints of fired transitions into firing domains of state classes, the computation of end-to-end delays can be performed synchronously with the evolution of state classes in the same firing rules. Therefore, the proposed method avoids the maintain of all visited state classes along an execution trace in the global set method, and is suitable for the on-the-fly verification of time properties based on time Petri nets.KeywordsEnd-to-end delay computationState classesTime Petri nets

The verification of real-time systems has been an active area of research for several decades now. Some results have been successfully transferred to industry. Still, many obstacles remain that hinder a smooth integration of academic research and industrial application. In this extended abstract, we discuss some of these obstacles and ongoing research and community efforts to bridge this gap. In particular, we present several experimental and theoretical methods to evaluate and compare real-time systems analysis methods and tools.

The article substantiates the directions of informatization of the modern educational process in the institution of general secondary education. The analysis of normative maintenance is carried out and the needs of science, education and culture in informatization of educational process are defined. The purpose of the article: to substantiate the theoretical foundations of informatization of educational institutions. Research methods are used: analysis of scientific developments on the problem and normative sources; generalization and systematization − to identify promising areas of informatization; generalization of semantic characteristics of directions − for formulation of conclusions. The main directions of use of computer and information technologies in the institution of general secondary education are characterized, among which Computer and information technologies as an object of study, computer as a means of teaching various disciplines, as a tool to support subject lessons and other activities, as a means of development and upbringing of the child, the use of computers to perform educational and real tasks and to implement various activities, Information Technology as a means of diagnosing various functional systems of the child's body. The following arguments regarding the use of computer technology in the educational process of the school are emphasized: computer technology contributes to the improvement of teaching and increase the effectiveness of teaching; Computer literacy should be developed as early as possible so that students get used to and can quickly adapt to the constant updating of computer technology; thanks to computer technology, including the Internet, the mobility of the educational process increases, namely: students can communicate with teachers and students of other educational institutions, as well as professionals from both domestic and other countries, without leaving their class; computer technologies promote the development of self-regulation and self-control, teach students to manage their intellectual activity. It is concluded that the advantages of informatization include the following: increased activation of students' learning activities and motivation to learn; the emphasis is shifted to the development of practical skills, the development of creative thinking, memory, etc., the creation of conditions for active cooperation, the development of creativity, to develop communication skills.

The design of modern real-time systems not only needs to guarantee their timing correctness, but also involves other critical metrics such as control quality and energy consumption. As real-time systems become increasingly complex, there is an urgent need for efficient optimization techniques that can handle large-scale systems. However, the complexity of schedulability analysis often makes it difficult to be directly incorporated in standard optimization frameworks, and inefficient to be checked against a large number of candidate solutions. In this paper, we propose a novel optimization framework for the design of real-time systems. It leverages the sustainability of schedulability analysis that is applicable for a large class of real-time systems. It builds a counterexample-guided iterative procedure to efficiently learn from an unschedulable solution and rule out many similar ones. Compared to the state-of-the-art, the proposed framework may be ten times faster while providing solutions with the same quality.

Within the framework of time verification of real time systems, we present a new technique for the reachability analysis of hybrid automata. We call this technique the Splitting Reachability Analysis. It is applied to a synchronized product of hybrid automata. The basic idea is to compute separately and simultaneously states sets in each component of a synchronized product of hybrid automata. The composition of these sets is an upper-approximation of the reachable states set of the synchronized product. Compared to a classical technique, the benefit, shown through with the example of the Fischer mutual exclusion protocol, is to reduce the costs in memory and computation time.

Weighted timed automata (WTA), introduced in Alur et al. (Proceedings of HSCC’01, LNCS, vol. 2034, pp. 49–62, Springer, Berlin, 2001), Behrmann et al. (Proceedings of HSCC’01, LNCS, vol. 2034, pp. 147–161, Springer, Berlin, 2001) are an extension of Alur and Dill (Theor. Comput. Sci. 126(2):183–235, 1994) timed automata, a widely accepted formalism for the modelling and verification of real time systems. Weighted timed automata extend timed automata by allowing costs on the locations and edges. There has been a lot of interest Bouyer et al. (Inf. Process. Lett. 98(5):188–194, 2006), Bouyer et al. (Log. Methods Comput. Sci. 4(2):9, 2008), Brihaye et al. (Proceedings of FORMATS/FTRTFT’04, LNCS, vol. 3253, pp. 277–292, Springer, Berlin, 2004), Brihaye et al. (Inf. Comput. 204(3):408–433, 2006) in studying the model checking problem of weighted timed automata. The properties of interest are written using logic weighted CTL (WCTL), an extension of CTL with costs. It has been shown Bouyer et al. (Log. Methods Comput. Sci. 4(2):9, 2008) that the problem of model checking WTAs with a single clock using WCTL with no external cost variables is decidable, while 3 clocks render the problem undecidable Bouyer et al. (Inf. Process. Lett. 98(5):188–194, 2006). The question of 2 clocks is open. In this paper, we introduce a subclass of weighted timed automata called weighted integer reset timed automata (WIRTA) and study the model checking problem. We give a clock reduction technique for WIRTA. Given a WIRTA $\mathcal{A}$ with n≥1 clocks, we show that a single clock WIRTA $\mathcal{A}'$ preserving the paths and costs of $\mathcal{A}$ can be obtained. This gives us the decidability of model checking WIRTA with n≥1 clocks and m≥1 costs using WCTL with no external cost variables. We then show that for a restricted version of WCTL with external cost variables, the model checking problem is undecidable for WIRTA with 3 stopwatch costs and 1 clock. Finally, we show that model checking WTA with 2 clocks and 1 stopwatch cost against WCTL with no external cost variables is undecidable, thereby answering a question that has remained long open.

Automatic Methods and Tools for the Verification of Real Time Systems