Splitting reachability analysis in hybrid automata

In this paper, we investigate the modeling and verification of real time systems using a case study on transmission protocol, CSMA/CD. Modeling and verification of real time systems is hot research topic which has practical implications. Such systems are considered as mission critical, as its correctness within timed constraints are of great importance. Through modeling and verifying CSMA/CD protocol using timed extension of CSP (TCSP) modeling techniques in PAT, we propose a formal model for CSMA/CD protocol and verify its critical properties like deadlock-freeness, divergence-freeness and collision detection in a given bounded delay. The integrated reduction techniques in PAT help in carrying out the verification with reasonable speed and results.

Real-time systems are used in many critical applications. Verification of these real-time systems is essential. Presented here is a method for modeling real-time systems and computing the model's timing characteristics automatically. From a data-driven model of the system an equivalent finite state machine representation of the system is produced by this package. To provide efficient traversal of this large state space an ordered binary decision diagram (OBDD) is used to represent the state machine using symbolic methods. Algorithms have been developed to find the largest and smallest distance (times) between any two state sets. From these algorithms schedulability of the real-time system can be determined.

An approach to the modeling and verification of real-time systems is presented. The Specification PEARL description language is used for hardware/software modeling. It has its origins in the standard Multiprocessor PEARL language. Its usefulness has been enhanced for asymmetrical multiprocessor system modeling, and parameters for schedulability analysis have been added. It is meant to be an over-layer for PEARL programs and supports the corresponding program model. The detailed program models are represented internally by timed state transition automata. The model of the co-designed system is verified for feasibility with co-simulation. The resulting information may be used for changes in the current design to gain a feasible model of the system. After that, the program models may be enhanced to their full functionality. Schedulability analysis, which should provide the designer with more precise information, can then be done. The new information can be reused on the system model in order to discover bottlenecks or possible discrepancies with the estimated times. By utilising this methodology, the possibility of implementing a non-feasible system should be minimised.

Weighted timed automata (WTA), introduced in Alur et al. (Proceedings of HSCC’01, LNCS, vol. 2034, pp. 49–62, Springer, Berlin, 2001), Behrmann et al. (Proceedings of HSCC’01, LNCS, vol. 2034, pp. 147–161, Springer, Berlin, 2001) are an extension of Alur and Dill (Theor. Comput. Sci. 126(2):183–235, 1994) timed automata, a widely accepted formalism for the modelling and verification of real time systems. Weighted timed automata extend timed automata by allowing costs on the locations and edges. There has been a lot of interest Bouyer et al. (Inf. Process. Lett. 98(5):188–194, 2006), Bouyer et al. (Log. Methods Comput. Sci. 4(2):9, 2008), Brihaye et al. (Proceedings of FORMATS/FTRTFT’04, LNCS, vol. 3253, pp. 277–292, Springer, Berlin, 2004), Brihaye et al. (Inf. Comput. 204(3):408–433, 2006) in studying the model checking problem of weighted timed automata. The properties of interest are written using logic weighted CTL (WCTL), an extension of CTL with costs. It has been shown Bouyer et al. (Log. Methods Comput. Sci. 4(2):9, 2008) that the problem of model checking WTAs with a single clock using WCTL with no external cost variables is decidable, while 3 clocks render the problem undecidable Bouyer et al. (Inf. Process. Lett. 98(5):188–194, 2006). The question of 2 clocks is open. In this paper, we introduce a subclass of weighted timed automata called weighted integer reset timed automata (WIRTA) and study the model checking problem. We give a clock reduction technique for WIRTA. Given a WIRTA $\mathcal{A}$ with n≥1 clocks, we show that a single clock WIRTA $\mathcal{A}'$ preserving the paths and costs of $\mathcal{A}$ can be obtained. This gives us the decidability of model checking WIRTA with n≥1 clocks and m≥1 costs using WCTL with no external cost variables. We then show that for a restricted version of WCTL with external cost variables, the model checking problem is undecidable for WIRTA with 3 stopwatch costs and 1 clock. Finally, we show that model checking WTA with 2 clocks and 1 stopwatch cost against WCTL with no external cost variables is undecidable, thereby answering a question that has remained long open.

Specification and verification of real-time systems are important research topics with crucial applications; however, the so-called state space explosion problem often prevents model checking to be used in practice for large systems. In this work, we present a self-contained toolkit to analyze real-time systems specified using event-recording automata (ERAs), which supports system modeling, animated simulation, and fully automatic compositional verification based on learning techniques. Experimental results show that our tool outperforms the state-of-the-art timed model checker.

The need of conceiving reliable real-time systems is crucial for the software engineering. This paper is dedicated to the specification and the verification of land transportation systems taken as an application domain. We present a case study in the area of transportation. The system consists of several automated vehicles called CyCab, that have to communicate with a station. The components are modeled with timed automata and some properties are expressed in the timed logic TCTL to be checked by the model checking tool Kronos. These systems, which are both distributed and embedded, require to express non functional-properties, for example a response time constrained.

Automatic Methods and Tools for the Verification of Real Time Systems

Neural Networks (NNs) can provide major empirical performance improvements for robotic systems, but they also introduce challenges in formally analyzing those systems’ safety properties. In particular, this work focuses on estimating the forward reachable set of closed-loop systems with NN controllers. Recent work provides bounds on these reachable sets, yet the computationally efficient approaches provide overly conservative bounds (thus cannot be used to verify useful properties), whereas tighter methods are too intensive for online computation. This work bridges the gap by formulating a convex optimization problem for reachability analysis for closed-loop systems with NN controllers. While the solutions are less tight than prior semidefinite program-based methods, they are substantially faster to compute, and some of the available computation time can be used to refine the bounds through input set partitioning, which more than overcomes the tightness gap. The proposed framework further considers systems with measurement and process noise, thus being applicable to realistic systems with uncertainty. Finally, numerical comparisons show that our approach based on linear programming and partitioning can give 10× reduction in conservatism in $\frac{1}{2}$ of the computation time compared to the state-of-the-art, and the ability to handle various sources of uncertainty is highlighted on a quadrotor model.

RTCP-nets are high level Petri nets similar to timed colored Petri nets, but with different time model and some structural restrictions. The paper deals with practical aspects of using RTCP-nets for modeling and verification of real-time systems. It contains a survey of software tools developed to support RTCP-nets. Verification of RTCP-nets is based on coverability graphs which represent the set of reachable states in the form of directed graph. Two approaches to verification of RTCP-nets are considered in the paper. The former one is oriented towards states and is based on translation of a coverability graph into nuXmv (NuSMV) finite state model. The later approach is oriented towards transitions and uses the CADP toolkit to check whether requirements given as μ-calculus formulae hold for a given coverability graph. All presented concepts are discussed using illustrative examples

For the Automata Theory Column, we have an article by B. Srivathsan on the reachability problem in timed automata. Ever since timed automata were introduced by Alur and Dill, they have been widely used in the verification of real-time systems. Their appeal comes from a simple definition that couples expressiveness with computational tractability. The control state reachability problem, which asks if there is a computation of a given timed automaton that reaches a given control state, is an important problem in this context and was shown to be decidable in PSPACE by Alur and Dill in their seminal paper. However, because of the central role this problem plays in verification, it has been extensively studied in the past 30 years. In this issue, Srivathsan lucidly articulates the main principles underlying modern approaches to solving this problem.

Advances in sensing, effecting, and computational technologies will change the way we design, construct, and monitor systems that interact with the physical world. Building structures will sense and respond to external loads, autonomous robots will occupy construction sites, and intelligent vehicles will monitor network flows to circumvent delays. As engineers, we must be prepared to work with the information technologies that underpin these coming systems. This paper addresses several of the prominent technical concerns in designing real-time systems that control some aspect of their environment. The view taken is that, by considering software systems to be an engineering artifact, we can begin to develop the kinds of quantitative approaches found in other areas of engineering design.

Time Petri nets are a powerful formal model for the specification and verification of real-time systems. End-to-end delays in task execution are a key requirement to real-time systems. In this paper, we propose a state class method based on time Petri nets for the computation of end-to-end delays. By introducing time constraints of fired transitions into firing domains of state classes, the computation of end-to-end delays can be performed synchronously with the evolution of state classes in the same firing rules. Therefore, the proposed method avoids the maintain of all visited state classes along an execution trace in the global set method, and is suitable for the on-the-fly verification of time properties based on time Petri nets.KeywordsEnd-to-end delay computationState classesTime Petri nets

Purpose Recent advancements in technology have enabled railway organizations to shift from manual to computer based automated interlocking systems for increasing their efficiency and profits. Since automated systems are complex and interlocking systems are safety critical systems, these systems should be modeled and verified against safety requirements to weed out any design bugs which might lead to catastrophes during their system life cycles. In this study, we model software based automated interlocking control system of a train station, located at Rawalpindi Cantt (Pakistan). Methods We have modeled software based automated interlocking control system using timed automata and verified its correctness using UPPAAL model checking software. Timed automata have successfully been used for the modeling and verification of real-time systems. Results We constructed a real-time model of railyard interlocking system by employing a model-checking approach to determine behavior of the model under various conditions. The model checker ascertains the absence of errors in a system by inspecting all the possible states or scenarios of the modeled system. The results show that important properties related to the safety of the designed interlocking system of the railyard management system can be verified using our presented approach. These properties ranged from collision and de-railment avoidance to checking the correct error handling functionality of the timed automata models. Conclusions The final modular design can easily adapt to the route upgrades and changes within the station by simple variable adjustments. Based on the laid down methodology and verification techniques, this study can be further built upon, extended and linked to cover the shunting aspect of the train station operations, run through operations, introducing automatic train stop (ATS) functionality and recommend three to four aspect traffic signaling for the train station. This study takes a first step in providing an indigenous solution to an indigenous problem of designing an upgraded and verified signaling infrastructure for Pakistan Railway’s Rawalpindi Cantt train station.

The specification of reactive and real-time systems must be supported by formal, mathematically-founded methods in order to be satisfactory and reliable. Temporal logics have been used to this end for several years. Temporal logics allow the specification of system behavior in terms of logical formulas, including temporal constraints, events, and the relationships between the two. In the last ten years, temporal logics have reached a high degree of expressiveness. Most of the temporal logics proposed in the last few years can be used for specifying reactive systems, although not all are suitable for specifying real-time systems. In this paper we present a series of criteria for assessing the capabilities of temporal logics for the specification, validation, and verification of real-time systems. Among the criteria are the logic's expressiveness, the logic's order, presence of a metric for time, the type of temporal operators, the fundamental time entity, and the structure of time. We examine a selection of temporal logics proposed in the literature. To make the comparison clearer, a set of typical specifications is identified and used with most of the temporal logics considered, thus presenting the reader with a number of real examples.

Areas of computer application are being broadened rapidly due to the rapid improvement of the performance of computer hardware. Applications that were not feasible before are now becoming feasible with high-performance computers. This results in increased demands for computer applications that are large and have complex temporal characteristics. Most analysis methods available, however, cannot handle large, complex real-time systems adequately; They do not scale-up, lack formalism to represent complex features and perform analyses with mathematical rigor, do not support analyses from different viewpoints, or are too hard to learn and apply. TVe need analysis methods that support formal specification and verification of real-time systems. Incremental performance of specification and analysis of systems from different viewpoints (e.g., user, analyst ) must also be supported with languages appropriate for each different viewpoint and for the users involved. This paper introduces a real-time systems analysis method, named PARTS, that aims at providing above features. PARTS supports analyses from two viewpoints: external viewpoint, a view of the sys-Permission tern from the user's perspective, and internal viewpoint, a view from the developer's perspective. These viewpoints are specified using formal languages, which are: Real-Time Events Trace (RTET) for the external viewpoint, and Time Enriched Statecharts (TES) and PARTS Data Flow Diagram (PDFD) for the internal viewpoint. All PARTS languages are based on the Real-Time Temporal Logic (RTTL), and consistency of the specifications made from two different viewpoints are analyzed based on the same RTTL formalism. PARTS converts RTET and TES specifications to RTTL specifications, which are then integrated and analyzed for consistency. All of the PARTS specificaticm languages support the top-down strategy to handle complexity.