Design challenges in building an advanced NAND flash array controller for 19/20 nm MLC

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Globalization of semiconductor industry has led to unprecedented challenges in design, verification, test, security and trustworthiness of contemporary electronics. With parts sourced from various suppliers across the globe, who are beyond the auspices of the original designers and system integrators, serious concerns arise regarding integrity and trustworthiness of electronic circuits, which can be compromised by malicious actors at any stage of the component manufacturing and system assembly process. Among the variety of such concerns, recycled electronics sold as new by malicious suppliers/vendors pose a key threat to mission-critical end applications such as military systems, financial institutions, transportation security, and poser distribution infrastructure. Recycled electronics may experience performance degradation due to aging and, more importantly, may have shorter-than-expected lifetime, thereby raising serious reliability and safety issues. To combat this problem, statistical methods have been proposed in the past decade as a time-efficient and cost-effective approach to identify recycled electronics sold as new. Initially demonstrating in the context of detecting recycled Integrated Circuits (ICs), such methods are based on using statistics and machine learning to outline the parametric signatures of known brand-new ICs and, thereby, weed out ICs that do not fit the expected profile. This article summarizes the current state of knowledge in recycled IC detection schemes and discusses how these methods have inspired, over time, the development of similar solutions in a plethora of domains, including identification of recycled Field Programmable Gate Arrays (FPGAs), recycled hardware components in a network, and recycled Static Random-Access Memories (SRAMs)/Flash memories</i> .

The thermal control system for a Venus Lander is critical to mission success and the harsh operating environment presents significant thermal design and implementation challenges. A successful thermal architecture draws heavily from previous missions to the Venus surface such as Pioneer Venus and the Soviet Venera Landers. Future Venus missions will require more advanced thermal control strategies to allow greater science return than previous missions and will need to operate for more than one or two hours as previous missions have done. This paper describes a Venus Lander thermal architecture including the technology development of a phase change material system for absorbing the heat generated within the Lander itself and an insulation system for resisting the heat penetrating the Lander from the Venus environment. The phase change energy storage system uses lithium nitrate that can absorb twice the amount of energy per unit mass in comparison to paraffin based systems. The insulation system uses a porous silica material capable of handling a high temperature and high pressure gas environment while maintaining low thermal conductivity.

As the flash cell physical size is scaled down, the related down scaling of decoder and page buffer area are also a challenge for chip design. High performance N type MOS including HVN_PT (in word-line decode circuit) and HVN_PB (in page buffer circuit) for l×-nm planner NAND flash are described in this paper. These N type MOS adopted a series of optimized structure and process integrated methods based on 2D TCAD process and device simulation, to achieve high channel, junction breakdown, and isolation voltage with smaller transistor area limited by down scaled NAND flash cell unit. Finally, these structure and process integrated methods were validated in HLMC 12-inch l×-nm NAND process flow.

This chapter discusses how to properly address the issues of using NAND flash memories as mass-memory devices from the native file system standpoint. We hope that the ideas and the solutions proposed in this chapter will be a valuable starting point for designers of NAND flash-based mass-memory devices.

This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon residues called stringers. The increase of polysilicon over-etching to eliminate stringers involves a trade-off between the removal efficiency of stringers and the feature size maintenance. Hence, a novel bottle-shaped gate profile was tailor-made and studied. As a result, the bridge rates are dramatically suppressed to 0%∼10% on the low-density flash cells and ca. 22% in average on the high-density 512 Mb flash cell memory. The novel bottle-shaped gate structure is successfully implemented in advanced charge-trapping flash memory development.

We report reproducible multibit transparent flash memory in which a single solution-derived Ta2O5 layer is used simultaneously as a charge-trapping layer and a tunneling layer. This is different from conventional flash memory cells where two different dielectric layers are typically used. Under optimized programming/erasing operations, the memory device shows excellent programmable memory characteristics with a maximum memory window of ∼10.7 V. Moreover, the flash memory device shows a stable 2-bit memory performance and good reliability, including data retention for more than 104 s and endurance performance for more than 100 cycles. The use of a common charge-trapping and tunneling layer can simplify the fabrication of advanced flash memories.

With reference to the mainstream technology, the most relevant failure mechanisms that affect reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The degradation of device. performance induced by program/erase cycling is discussed, specifically for what concern the leakage that affect a very small fraction of memory cells after cycling. The dependence of the leakage on tunnel oxide thickness, number of cycles, and temperature is analyzed. The leakage current is explained by trap-assisted tunneling involving one, two or more traps, with decreasing occurrence probability. Finally, data are presented showing the robustness of scaled Flash memory to alpha particles and electromagnetic radiation.

As the power dissipation has become one of the critical design challenges in a sensor network environment, non- volatile memories such as STT-MRAM and flash memory will be used in the next generation sensor nodes. In this paper, we studied an efficient buffer management scheme considering the write limitation of STT-MRAM based main memory as well as the erase-before-write limitation of flash memory for storage device. The goal of proposed scheme is to minimize the number of write operations on STT- MRAM as well as the number of erase operations on flash memory. We showed through simulation that proposed scheme outperforms legacy buffer management schemes. Index Terms - Non-volatile memories, Low power, Buffer management, STT-MRAM, NAND flash memory.

Emerging data-intensive applications with frequent small random read operations challenge the throughput capabilities of conventional SSD architectures. Although Compute Express Link enabled SSDs allow for fine-grained data access with reduced latency, their read throughput remains limited by legacy block-oriented designs. To address this, we propose srNAND, an advanced NAND flash architecture for CXL SSDs. It uses a twostage ECC decoding mechanism to reduce read amplification, an optimized read command sequence to boost parallelism, and a request merging module to eliminate redundant operations. Our evaluation shows that srSSD can improve read throughput by up to 10.4× compared to conventional CXL SSDs.

Continuous improvement in hardware design and advances in wireless communication have enabled the deployment of various wireless sensor applications. Though, sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Flash memory has become a more widespread storage medium for modern wireless devices because of its effective features like nonvolatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Even though flash memory offers many advantages, its special hardware read, write and erase characteristics impose design challenges on storage systems. This survey analysis the flash based storage management techniques proposed for resource constraint sensor devices, in terms of data life, device life, energy, and storage efficiency. Comprehensive simulation results show gradually improved performance in area of wireless sensor networks.

Certain NAND flash-based storage devices are not equipped with dynamic random access memory (DRAM) for holding the whole mapping table, due to the constraints of chip size and the cost, such as secure digital cards. Such DRAM-less flash memory can load only a subset of frequently accessed mapping table entries into a limited-capacity, on-board static random access memory (SRAM) cache, to expedite address translation. To improve the use efficiency of the SRAM cache, this paper proposes to prefetch mapping table entries into the cache according to their locality . Then, it can minimize the number of translation page reads at the flash array caused by loading the required entries, thus improving I/O performance. Specifically, we use the indicator of runs test to reflect the locality of mapping table entries on the same translation page. When processing a missed mapping entry, it determines whether adjacent mapping entries accompanying the missed one should be loaded into the cache or not, on the basis of the runs of the target translation page. Consequently, subsequent requests requiring access to these mapping entries can be quickly responded to with the cached ones, instead of reading the target translation pages. In addition, we support cache management based on the runs test of the mapping entries to further improve the cache hit ratio. Experimental results show that our proposal can increase the hit ratio of mapping table entries by 39.4 % and reduce overall I/O latency by 23.4 % on average, in contrast to state-of-the-art schemes.

This paper presents the evaluation methods and findings of the hot temperature embedded erase failure on an embedded NOR flash EEPROM device. Automated Test Equipment (ATE) and bench evaluation revealed that the embedded erase failure was caused by compaction failure with high compaction pulse counts. Failure localization using memory bitmapping showed that the fail bitcells were populated at the edge of the flash array. Based on detailed electrical characterization and physical analysis, compaction failure was determined to be due to poor hot carrier injection (HCI) efficiency as a result of possible shallow trench isolation (STI) over-polish.

Predictable latency on flash storage is a long-pursuit goal, yet, unpredictability stays due to the unavoidable disturbance from many well-known SSD internal activities. To combat this issue, the recent NVMe IO Determinism (IOD) interface advocates host-level controls to SSD internal management tasks. While promising, challenges remain on how to exploit it for truly predictable performance. We present IODA, an I/O deterministic flash array design built on top of small but powerful extensions to the IOD interface for easy deployment. IODA exploits data redundancy in the context of IOD for a strong latency predictability contract. In IODA, SSDs are expected to quickly fail an I/O on purpose to allow predictable I/Os through proactive data reconstruction. In the case of concurrent internal operations, IODA introduces busy remaining time exposure and predictable-latency-window formulation to guarantee predictable data reconstructions. Overall, IODA only adds 5 new fields to the NVMe interface and a small modification in the flash firmware, while keeping most of the complexity in the host OS. Our evaluation shows that IODA improves the 95-99.99th latencies by up to 75x. IODA is also the nearest to the ideal, no disturbance case compared to 7 state-of-the-art preemption, suspension, GC coordination, partitioning, tiny-tail flash controller, prediction, and proactive approaches.

Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional. Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause. The erratic Vmin phenomenon can be eliminated for 90 nm SRAMs by process optimization. However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array. A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling

In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory (NUC-CTM) device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect (SBE) and provide 3-bit per cell capability. Owing to the n− buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.