Design methodologies, models and tools for very-large-scale integration of NEM relay-based circuits

Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design space and the time required for detailed cycle-accurate simulations. The proposed design framework takes as inputs the design targets (upper bounds on execution time, area, and energy), design alternatives, and one or more application programs. The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area. The core of the new design framework is made up of analytical performance and energy activity models, and an analytical model-based design optimization process.For a set of benchmark programs and a design space of 2000 designs, the design framework arrives at all performance-energy-area Pareto-optimal design points within 16 minutes on a 2 GHz Pentium-4. In contrast, it is estimated that a naive cycle-accurate simulation-based exhaustive search would require at least two months to arrive at the Pareto-optimal design points for the same design space.

EXTENDED ABSTRACT The development of high density 2.5D and 3D TSV chip stacking technology is rapidly moving forward, with the establishment of prototype fabrication lines, assembly and test of demonstrator test vehicles, and characterization and engineering reliability data now available. Several chip stacking partitions are reportedly in development for productization, examples of which are shown in Figure 1. Development of JEDEC-standard wide IO DRAM is also proceeding, which will enable high bandwidth at low power. Wide IO DRAM can be stacked as a single die or as Micro Pillar Grid Array (MPGA) cubes either directly on logic die or side by side on a TSV interposer. Heterogeneous stacking of logic die on logic die fabricated in different technology nodes offers compelling opportunities for cost savings and design re-use. 2.5D TSV interposers are likely to be the first partition to be productized, since TSVs are only required in the inactive interposer and not in the chips with active circuits. Considerable knowledge has been gained with respect to previously perceived challenges, including high aspect ratio (~10:1) via formation, backside wafer processing, microjoining, test/DFT, thermal/mechanical integrity, design methodologies, and intrinsic reliability. Integrated process modules for via-middle formation, including high aspect ratio silicon etch, liner and barrier/seed deposition, copper fill, and CMP overburden removal, and for tier to tier microjoining, are now established. Backside wafer processing, including temporary carrier mount and demount processes, have been successfully demonstrated and continue to be refined. Engineering reliability data collected from test vehicles has been used to identify reliability risks such as TSV copper pumping, driving process optimization to eliminate the failure modes and implementation of design rule constraints. Thermal and mechanical integrity challenges associated with TSV chip stacking are highly dependent on the particular component and system-level design. Design-for-Thermal methodologies and the use of mechanical stress simulators are being developed to manage these interactions. ASIC Design and test/DFT methodology requirements are contingent on the specific system partition implemented. Designs with properly constrained partitions will require only limited extensions to existing 2D design methodologies and EDA tools. Especially critical for the productization of high density TSV technology for high volume mobile wireless applications will be the readiness of the fabless supply chain infrastructure, including industry standards, supply chain business models for stacked memory cubes, and competitive pricing. Initial adoption of this disruptive new technology will depend on offering a compelling technical and business value proposition which cannot be attained by extending existing technical solutions.

One of the main problems in design of modem microelectronic systems is achieving consistent high quality results along the entire EDA tool chain. Using the sequential logic synthesis tools for a case study, this paper shows how important is the consistent tool collaboration for the quality of the final result. In the paper, a new uniform and consistent information-driven logic synthesis approach is proposed and compared to some other logic synthesis flows, including the traditional flow involving JEDI and SIS. The experimental research demonstrates that the quality of the new information-driven logic synthesis tools and the harmony of the new uniform approach results in much better circuits than the circuits from all other flows. The information-based synthesis flow produced circuits that are on average 25% smaller and 30% faster than the circuits from traditional flow.

This paper deals with problems involving the incorporation of safety into the design process of large marine and offshore engineering products from the initial stages. In this paper, the characteristics of large marine and offshore products are described and their design process is studied together with a proposed design framework. After investigating the current design for safety status of large marine and offshore products, a design for safety methodology is proposed in a generic sense and discussed in the context of the design process. The phases in the proposed design for safety methodology are studied together with their objectives and requirements. Finally, concluding remarks are given.

Modern VLSI systems are under strict power and performance constraints, and the trade-offs between these two aspects drive industry and academic research alike. Static CMOS has been the leading logic family used in commercial VLSI systems for over a decade, but many alternatives exists and are currently being investigated. For example, some approaches propose to replace the kind of transistor devices used (e.g. TFET instead of MOSFET), or to use different materials (e.g. carbon nanotubes instead of silicon). At a higher level in the circuit design taxonomy, different logic families have been investigated (Dynamic circuits, Pass-transistor circuits, et cetera). A promising logic family, targeted at low-power consumption, is Charge Recovery Logic, or CRL, also known as adiabatic logic. CRL is a logic style aimed at reducing power consumption by recycling energy, and has been a growing topic of academic research for the past two decades. On one hand, CRL requires a paradigm shift in logic synthesis and design automation, and to this day no Electronic Design Automation tools exist that can take advantage of CRL's unique characteristics: The creation of such a tool needs methods and algorithms tailored to CRL. On the other hand, CRL energy-saving principles can be extended to mixed-signal circuits, e.g. comparators: this creates the new category of Charge Recovery Circuits. The union of the aforementioned fields of inquiry paves the road to fully adiabatic System-on-Chip (SOCs). This PhD dissertation presents results and methods that support the development of charge recovery SOCs. In the first part, CRL-specific algorithms are used to synthesize and compile large combinational logic circuits. Transistor-level simulations show that charge recovery logic is a feasible candidate to replace static CMOS for low-energy applications. In addition to these results, an EDA tool has been developed to provide the academic community with unprecedented access to system-level research. In the second part, an adiabatic analog comparator and a fully-adiabatic analog-to-digital-converter (ADC) are presented. Results show that the adiabatic principles can be successfully used to decrease the energy of mixed-signal circuits as well, with low impact on performance.

To transmit the teaching of digital electronics today, considerations are outlined which must be kept in mind. Digital electronics is evolving quickly and its techniques and tools have revolutionized the manner of analyzing simulating, synthesizing and verifying digital systems. Microelectronic development is more and more dependant on the technology and on design methodology. Standard hardware description languages (Verilog and VHDL), together with simulation and synthesis tools are some of the drivers behind microelectronic development. The constructivist model in the teaching-learning process proposes: significant learning as opposed to memorizing; structuring and sequencing of content; learning through guided discovery and a spiral or recurring procedure. These circumstances, together with pedagogical concern and the knowledge and experience that the authors have acquired as digital electronics teaching Professors have resulted in the formulation of a curricular proposal to transmit this updated teaching method. Using this teaching model as a base, the aim of the proposal is to have the student studying digital electronics acquire the theory and practices (know-how) from the beginning by using current design methodologies and CAD and EDA tools that the students will use in their professional future. Another objective of this method is to provide students with multimedia applications as a learning resource.

In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality design tool architecture, and design methodology are explored.

Chiplet technology has emerged as a transformative approach in integrated circuit design. Although it has attracted significant attention recently, there has been limited effort dedicated to clearly defining its concept, terminology, composition, and evolution phases etc. This survey paper gives a formal definition by proposing chiplet terminology and composition, name it as a new design methodology, then analyze over 200 recent publications from both academia and industry to establish chiplet as a technology domain composed of four distinct fields: chiplet-based SoC architecture, interconnect, EDA tools, and advanced packaging. For each field composing chiplets, the paper traces the technology development, analyze challenges, outline the evolution trend and challenges. This survey aims to provides an in-depth examination of chiplet domain and each field’s progress, offering insights drawn from literature analysis to outline the current and emerging landscape of chiplet technology.

Design-based equivalent scaling now bears much of the burden of continuing the semiconductor industry's trajectory of Moore's-Law value scaling. In the future, reductions of design effort and design schedule must comprise a substantial portion of this equivalent scaling. In this context, machine learning and deep learning in EDA tools and design flows offer enormous potential for value creation. Examples of opportunities include: improved design convergence through prediction of downstream flow outcomes; margin reduction through new analysis correlation mechanisms; and use of open platforms to develop learning-based applications. These will be the foundations of future design-based equivalent scaling in the IC industry. This paper describes several near-term challenges and opportunities, along with concrete existence proofs, for application of learning-based methods within the ecosystem of commercial EDA, IC design, and academic research.

Motor rehabilitation helps impaired patients to regain their motor skills. Video game based therapies are an alternative form of rehabilitation claiming higher therapy adherence. Demands from medical, technical and user centered perspectives have thus far guided the development of these systems. Designing a single game complying with all the suggested principles remains unsolved. A common solution is to create collections of games, each one partially addressing a few demands, but even the design of each individual game is still challenging. Here, the COMFeeDY (Concept, objects, mechanics, feedback, and dynamics) framework is proposed as a response to the need of creating game-based rehabilitation systems composed of a variety of video games in a simpler, reusable, and faster way. The use of the framework is illustrated through the design of a game for upper limb rehabilitation. The current proposal represents the seed to what we envisaged should grow into a full framework further incorporating the medical and user centered principles so that games developed under the framework would have better chances of being therapeutically valid from onset. By using the proposed design framework, it is expected that the design process can be speeded up, components can be reused, and the development of these games be simplified.

Joint linear beamforming and scheduling are performed in a system where limited feedback is present at the transmitter side. The feedback conveyed by each user to the base station consists of channel direction information (CDI) based on a predetermined codebook and a scalar metric with channel quality information (CQI) used to perform user scheduling. In this paper, we present a design framework for scalar feedback in MIMO broadcast channels with limited feedback. An approximation on the sum rate is provided for the proposed family of metrics, which is validated through simulations. For a given number of active users and average SNR conditions, the base station is able to update certain transmission parameters in order to maximize the sum-rate function. On the other hand, the proposed sum-rate function provides a means of simple comparison between transmission schemes and scalar feedback techniques. Particularly, the sum rate of SDMA and time division multiple access (TDMA) is compared in the following extreme regimes: large number of users, high SNR, and low SNR. Simulations are provided to illustrate the performance of various scalar feedback techniques based on the proposed design framework.

A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for many years to come. 2.5D/3D technology introduces a new degree of electrical design complexity which is unfamiliar to many existing electrical design methodologies and EDA tools. A new electrical verification methodology must be developed with consideration to the micro level (TSV and interposer structures) and macro/system level simulation. At the Micro level, modeling of TSV is challenging due to its dependency on the material properties of the medium surrounding it and its impact on the signal losses/attenuation, capacitance effects, and the coupling among the vertical interconnects. At the Macro level, new electrical characteristics of the system need to be closely coupled with the thermal and mechanical tolerances of the entire 2.5D/3D packaging structure in order for its ultra wideband data exchange between logic chip and memory chips. TSV placement on logic and memory chips must be carefully placed during the chip design placement stage in order to avoid unnecessary electromagnetic coupling and faulty logic latching. Traditional separate signal and power integrity analysis methodologies are no longer sufficient due to the close proximity of the power and signal distribution network. In order to accurately predict the performance of 2.5D/3D packages, a new design paradigm shift is needed to toggle 2.5D/3D system performance optimization. New design and modeling approaches along with new breeds of computational electromagnetic EDA tools, are paramount to predicting the performance of 2.5D/3D packages.

BackgroundSerious games are increasingly used at all levels of education. However, research shows that serious games do not always fulfill all the targeted pedagogical objectives. Designing efficient and engaging serious games is a difficult and multidisciplinary process that requires a collaborative approach. Many design frameworks have been described, most of which are dedicated to the development of specific types of serious games and take the collaborative dimension into account only to a limited extent.ObjectiveOur aim was to create a generic serious game design framework that could be adapted to all kinds of serious games and implemented in a collaborative web platform.MethodsWe combined the results of a literature review with our experience in serious game design and development to determine the basic building blocks of a collaborative design framework. We then organized these building blocks into categories and determined the features that a generic design framework should include. Finally, based on the paradigm of complex systems and systemic modelling, we created the co.LAB generic design framework and specifications to allow its implementation in a collaborative web platform.ResultsBased on a total of 10 existing design methodologies or frameworks, 23 building blocks were identified and represent the foundation of the co.LAB framework. These blocks were organized into 5 categories: “context and objectives,” “game design,” “mechanics,” “learning design,” and “assessment.” The arrangement by categories provides a structure that can be visualized in multiple and complementary ways. The classical view links game and learning design while other views offer project, systemic, and process visualizations. For the implementation of the co.LAB framework in a web platform, we propose to convert the building blocks into “cards.” Each card would constitute a collaborative working space for the design of the corresponding block. To make the framework adaptive, cards could be added, adapted, or removed according to the kind of serious game intended. Enhancing the visualization of relationships between cards should support a systemic implementation of the framework.ConclusionsBy offering a structured view of the fundamental design elements required to create serious games, the co.LAB framework can facilitate the design and development of such games by virtue of a collaborative, adaptive, and systemic approach. The different visualizations of the building blocks should allow for a shared understanding and a consistent approach throughout the design and development process. The implementation of the co.LAB framework in a collaborative web platform should now be performed and its actual usability and effectiveness tested.

PurposeThis paper seeks to highlight the role of entrepreneurship education in encouraging the growth of graduate entrepreneurship in the UK to help overcome the over‐supply of university graduates in a very difficult employment market. This paper aims to discuss the design principle for entrepreneurship education that facilitates graduate entrepreneurship, and the design methodology that allows multi‐faculty collaboration in the provision of entrepreneurship programmes.Design/methodology/approachThis paper begins with the conceptualisation of design principles and frameworks based on current concepts found in the literature, followed by practitioner‐based reflection to shed insights into the process of developing entrepreneurship education in higher education institutions (HEIs).FindingsThe authors have developed the “30/70 methodology” to guide the future design of entrepreneurship education, and the “80/20 methodology” to support cross‐faculty entrepreneurship programmes to serve non‐business students. Factors that impede or support academic entrepreneurship and effective integration of entrepreneurship programmes in HEIs are discussed.Originality/valueThis paper shares the authors' experiences, and their unique design principles and methodology to support the development of education for entrepreneurship.

This paper investigates a generalized homogeneous adaptive stabilization method for a class of high-order nonlinear systems without controllable/observable linearizations. Based on a general approximated homogeneous function restraining hypothesis, a series of quasi-homogeneous adaptive virtual controllers are built. By modifying the homogenous domination approach, an inductive stability analysis as well as the guideline of update laws is carried out in an explicit way. Furthermore, based on the proposed design framework, the asymptotical and finite-time stabilization with the flexibility of tuning homogeneous degree are investigated. Numerical simulations and a real example are presented to demonstrate the effectiveness of the proposed method.