Automated design of application specific superscalar processors

Optimizing processors for specific application(s) can substantially improve energy-efficiency. With the end of Dennard scaling, and the corresponding reduction in energyefficiency gains from technology scaling, such approaches may become increasingly important. However, designing applicationspecific processors require fast design space exploration tools to optimize for the targeted application(s). Analytical models can be a good fit for such design space exploration as they provide fast performance estimations and insight into the interaction between an application's characteristics and the micro-architecture of a processor. Unfortunately, current analytical models require some microarchitecture dependent inputs, such as cache miss rates, branch miss rates and memory-level parallelism. This requires profiling the applications for each cache and branch predictor configuration, which is far more time-consuming than evaluating the actual performance models. In this work we present a micro-architecture independent profiler and associated analytical models that allow us to produce performance and power estimates across a large design space almost instantaneously. We show that using a micro-architecture independent profile leads to a speedup of 25× for our evaluated design space, compared to an analytical model that uses micro-architecture dependent profiles. Over a large design space, the model has a 13% error for performance and a 7% error for power, compared to cycle-level simulation. The model is able to accurately determine the optimal processor configuration for different applications under power or performance constraints, and it can provide insight into performance through cycle stacks.

Integrated circuits based on nano-electro-mechanical (NEM) relays are a promising alternative to conventional CMOS technology in ultra-low energy applications due to their (near) zero stand-by energy consumption. Here we describe the details of an overarching design framework for NEM relays, including automated synthesis from design entry in RTL to layout, based on commercially available EDA tools and engines. Critical differences between relays and FETs manifest in fundamentally different timing characteristics, which significantly affect static timing analysis and the requisite timing models. The adaptation of existing EDA methods, models, tools and platforms for logic and physical synthesis to account for these differences are described, providing insight into large-scale design of NEM relay-based digital processors. A historically well-known processor, the Intel 4004, and a modern MIPS32 compatible processor are synthesized based on a NEM relay-based standard cell library to demonstrate the customized synthesis methodology. An energy study is carried out using the proposed design framework on benchmark circuits implemented in existing CMOS nodes and NEM node, to better understand the energy saving potential of NEM technology.

article Free Access Share on Framelets—small and loosely coupled frameworks Authors: Wolfgang Pree Univ. of Constance, Constance, Germany Univ. of Constance, Constance, GermanyView Profile , Kai Koskimies Nokia Research Center, Helsinki, Finland Nokia Research Center, Helsinki, FinlandView Profile Authors Info & Claims ACM Computing SurveysVolume 32Issue 1esMarch 2000 pp 6–eshttps://doi.org/10.1145/351936.351942Online:01 March 2000Publication History 10citation1,009DownloadsMetricsTotal Citations10Total Downloads1,009Last 12 Months7Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Given the rapid expansion in cloud computing in the past few years, there is a driving necessity of having cloud workloads running on a backend servers analyzed and characterized for performance and power consumption. In this research, we focus on Hadoop framework and Memcached, which are distributed model frameworks for processing large scale data intensive applications for different purposes. Hadoop is used for short jobs requiring low response time; it is a popular open source implementation of MapReduce for the analysis of large datasets, while Memcached is a high performance distributed memory object caching system that could speed up throughput of web applications by reducing the effect of bottlenecks on database load. In this paper, we characterize different workloads running on Hadoop framework and Memcached for different processor configurations and microarchitecture parameters. We implement an analytical estimation model for performance and power using different server processor microarchitecture parameters. The proposed analytical estimation model uses analytical method to scale different processor microarchitecture parameters such as CPI with respect to processor core frequency. We also propose an analytical model to estimate power consumption scaling for different processor core frequency. The combination of both performance and power consumption analytical models enables the estimation of performance per watt for different cloud benchmarks. The proposed estimation models are verified to estimate power and performance with less than 10% error deviation.

This study describes the use of an analytical model, constructed using sequential design of experiments (DOEs), to optimize and quantify the uncertainty of a Diesel engine operating point. A genetic algorithm (GA) was also used to optimize the design. Three engine parameters were varied around a baseline design to minimize indicated specific fuel consumption (ISFC) without exceeding emissions (NOx and soot) or peak cylinder pressure constraints. An objective merit function was constructed to quantify the strength of designs. The engine parameters were start of injection (SOI), injection duration, and injector included angle. The engine simulation was completed with a sector mesh in the commercial computational fluid dynamics (CFD) software CONVERGE, which predicted the combustion and emissions using a detailed chemistry solver with a reduced mechanism for n-heptane. The analytical model was constructed using the SmartUQ software using DOE responses to construct kernel emulators of the system. Each emulator was used to direct the placement of the next set of DOE points such that they improve the accuracy of the subsequently generated emulator. This refinement was either across the entire design space or a reduced design space that was likely to contain the optimal design point. After sufficient emulator accuracy was achieved, the optimal design point was predicted. A total of 5 sequential DOEs were completed, for a total of 232 simulations. A reduced design region was predicted after the second DOE that reduced the volume of the design space by 96.8%. The final predicted optimum was found to exist in this reduced design region. The sequential DOE optimization was compared to an optimization performed using a GA. The GA was completed using a population of 9 and was run for 71 generations. This study highlighted the strengths of both methods for optimization. The GA (known to be an efficient and effective method) found a better optimum, while the DOE method found a good optimum with fewer total simulations. The DOE method also ran more simulations concurrently, which is an advantage when sufficient computing resources are available. In the second part of the study, the analytical model developed in the first part was used to assess the sensitivity and robustness of the design. A sensitivity analysis of the design space around the predicted optimum showed that injection duration had the strongest effect on predicted results, while the included angle had the weakest. The uncertainty propagation was studied over the reduced design region found with the sequential DoE in the first part. The uncertainty propagation results demonstrated that for the relatively large variations in the input parameters, the expected variation in the ISFC and NOx results were significant. Finally, the predictions from the analytical model were validated against CFD results for sweeps of the input parameters. The predictions of the analytical model were found to agree well with the results from the CFD simulation.

Vector can enhance peak performance while multi-threading can improve efficiency. MTV is a new architecture that combines the two to achieve both high computing performance and high throughput. Matrix multiplication is the kernel of many scientific applications. A parallel matrix multiplication algorithm is presented and an analytical performance model is built. Based on the model, the performance of MTV was evaluated and critical configurations are given to guide the design of MTV processors..

One class of applications envisaged for the IEEE 802.15.4 LR-WPAN (low data rate--wireless personal area network) standard is wireless sensor networks for monitoring and control applications. In this paper we provide an analytical performance model for a network in which the sensors are at the tips of a star topology, and the sensors need to transmit their measurements to the hub node so that certain objectives for packet delay and packet discard are met. We first carry out a saturation throughput analysis of the system; i.e., it is assumed that each sensor has an infinite backlog of packets and the throughput of the system is sought. After a careful analysis of the CSMA/CA MAC that is employed in the standard, and after making a certain decoupling approximation, we identify an embedded Markov renewal process, whose analysis yields a fixed point equation, from whose solution the saturation throughput can be calculated. We validate our model against ns2 simulations (using an IEEE 802.15.4 module developed by Zheng [14]). We find that with the default back-off parameters the saturation throughput decreases sharply with increasing number of nodes. We use our analytical model to study the problem and we propose alternative back-off parameters that prevent the drop in throughput. We then show how the saturation analysis can be used to obtain an analytical model for the finite arrival rate case. This finite load model captures very well the qualitative behavior of the system, and also provides a good approximation to the packet discard probability, and the throughput. For the default parameters, the finite load throughput is found to first increase and then decrease with increasing load. We find that for typical performance objectives (mean delay and packet discard) the packet discard probability would constrain the system capacity. Finally, we show how to derive a node lifetime analysis using various rates and probabilities obtained from our performance analysis model.

A production line is an important class of manufacturing system when large quantities of identical or similar products are to be produced. The performance of a production line is highly influenced by machine failures. When a machine fails, it is then be unavailable during a certain amount of time required to repair it. Analysis of production lines divides into three types: analytical, approximation and simulation models. The analytical and approximation models have assumptions, which make these models unrealistic such as reliable workstations, certain processing distribution, the first workstation cannot be starved and the last workstation cannot be blocked. The main problems in production lines treatment are the calculation of throughput and average levels of buffers because of the great size of state space. An analytical model is reviewed to clarify the limitations to use such treatment in real production lines. Simulation modeling of production lines is considered very important for designers interested in: Workload Allocation Problem (WAP), Server Allocation Problem (SAP), and Buffer Allocation Problem (BAP). This paper studies and analyzes the performance keys, which effect on production lines. A simulation model is developed by using ARENA software and used to analyze and test several bottlenecks that are causing severe congestions in different areas on the production line and could resolve all of these bottlenecks. In this paper, an actual cement production line is used as a case study. After a simulation time of 13 days, a simulation results show the line bottlenecks, workstations utilization, buffer capacities and the line production rate. The outputs clarify redesign of allocation of buffers, which verify an optimum size could be made; it might be taken into consideration when designers implement such lines. Finally modified better workstations utilization, buffer capacities and the line production rate with an increase about 15% of the production rate and economizing of 37 % from buffer capacities

Graphics processing units (GPUs) have shown increased popularity and play an important role as kind of coprocessor in heterogeneous co-processing environment. Heavily data parallel problems can be solved efficiently due to tens of thousands threads collaborative work in parallel GPU architecture. The achieved performance, therefore, depends on the capability of multiple threads in parallel collaboration. This paper, a static analytical kernel performance model (SAKP) was proposed to estimate the execution time of GPU kernel. Especially, a set of kernel and device features for target GPU is generated in the proposed model. We determine the performance limiting factors and generate an estimation of kernel execution time with this model. Matrix multiplication (MM) and histogram generation (HG) in NVIDIA GTX680 GPU card were performed to verify our proposed model and showed an absolute error in prediction less than 6.8%.

Expanding the term “Design Space” in high performance liquid chromatography (I)

Due to the increasing gap between CPU and memory speed, cache performance plays an increasingly critical role in determining the overall performance of microprocessor systems. One of the important factors that a affect cache performance is the cache replacement policy. Despite the importance, current analytical cache performance models ignore the impact of cache replacement policies on cache performance. To the best of our knowledge, this paper is the first to propose an analytical model which predicts the performance of cache replacement policies. The input to our model is a simple circular sequence profiling of each application, which requires very little storage overhead. The output of the model is the predicted miss rates of an application under different replacement policies. The model is based on probability theory and utilizes Markov processes to compute each cache access' miss probability. The model realistic assumptions and relies solely on the statistical properties of the application, without relying on heuristics or rules of thumbs. The model's run time is less than 0.1 seconds, much lower than that of trace simulations. We validate the model by comparing the predicted miss rates of seventeen Spec2000 and NAS benchmark applications against miss rates obtained by detailed execution-driven simulations, across a range of different cache sizes, associativities, and four replacement policies, and show that the model is very accurate. The model's average prediction error is 1.41%,and there are only 14 out of 952 validation points in which the prediction errors are larger than 10%.

Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-flight instructions to exploit higher instruction level parallelism (ILP). Multiple ports for a register file are necessary to support execution of multiple instructions each cycle. These necessities lead to a larger register access time. However, register access time has to be minimal to enable design of high frequency processors. Analysis of lifetime of a logical to physical register mapping reveals that there are long latencies between the times a physical register is allocated, consumed, and released. We propose a dual bank register file organization that exploits such long latencies, resulting in a large bandwidth with a reduced register access time. Implementation of one flavor of the proposed register file organization, as compared to a conventional monolithic register file, in an 8-wide out-of-order issue superscalar processor enhanced instructions per cycle (IPC) throughput up to 6% for Spec2000 applications while inducing register access time up to 22%. Another flavor of the register file organization, with a similar access time as the conventional monolithic register file, enhanced the IPC up to 15%. Thus a trade-off between register access time and ILP exploitation is shown.

Multimedia applications are compute intensive applications that often contain multiple streams of operations such as audio and video running in parallel. These characteristics make them suitable for multi-stream processing through the use of parallel processing. In the first part of the thesis we evaluate the instruction and data bandwidth requirements of typical signal processing and multimedia functions. In the second part of the thesis we compare the advantages and disadvantages of programmable and algorithm specific integrated circuit digital signal processors. In order to accommodate the high level of instruction and data bandwidth found in multimedia applications we propose a superscalar digital signal processor (DSP) that can execute multiple instructions in parallel. A second feature of the proposed DSP is scalability. Scalability is an important feature needed to accommodate future increases in the performance requirements of multimedia applications. Our proposed DSP is also compatible with existing instruction-set architectures which eliminates the need for a specialized compiler. Next, we introduce a detailed analysis of the availability and distribution of instruction-level parallelism in ten existing multimedia applications. We also discuss the relationship between instruction-level parallelism and machine parallelism. In the following part of the thesis, we discuss machine parallelism and describe the different superscalar techniques used to fetch, decode, and execute multiple instructions per cycle. These techniques include out-of-order issue with out-of- order completion, register renaming, and branch prediction. A parameterizable superscalar simulator is used to simulate ten real-world multimedia applications on five different models of parallelism. The five models represent a wide range of machine parallelism, from a bare scalar machine to an ideal superscalar machine with unlimited parallelism. Results of the instruction- level parallelism study show that the multimedia benchmarks simulated contain a high level of parallelism in their code which make them suitable candidates for multiple-issue machines. In addition, this high level of instruction parallelism proves to be evenly distributed throughout the program which helps in maintaining a good balance between available parallelism and on-chip resources. Furthermore, machine parallelism simulation results show that instruction fetching places the ultimate limit on speedup and is the most critical factor in determining overall performance. However, by using aggressive branch prediction mechanisms and out-of-order issue with out-of-order completion techniques we are able to obtain a two to four fold increase in performance compared to a single issue scalar machine. Overall results show that abundant instruction parallelism combined with adequate machine parallelism proves to be a real performance booster for multimedia applications.

Motor rehabilitation helps impaired patients to regain their motor skills. Video game based therapies are an alternative form of rehabilitation claiming higher therapy adherence. Demands from medical, technical and user centered perspectives have thus far guided the development of these systems. Designing a single game complying with all the suggested principles remains unsolved. A common solution is to create collections of games, each one partially addressing a few demands, but even the design of each individual game is still challenging. Here, the COMFeeDY (Concept, objects, mechanics, feedback, and dynamics) framework is proposed as a response to the need of creating game-based rehabilitation systems composed of a variety of video games in a simpler, reusable, and faster way. The use of the framework is illustrated through the design of a game for upper limb rehabilitation. The current proposal represents the seed to what we envisaged should grow into a full framework further incorporating the medical and user centered principles so that games developed under the framework would have better chances of being therapeutically valid from onset. By using the proposed design framework, it is expected that the design process can be speeded up, components can be reused, and the development of these games be simplified.

Joint linear beamforming and scheduling are performed in a system where limited feedback is present at the transmitter side. The feedback conveyed by each user to the base station consists of channel direction information (CDI) based on a predetermined codebook and a scalar metric with channel quality information (CQI) used to perform user scheduling. In this paper, we present a design framework for scalar feedback in MIMO broadcast channels with limited feedback. An approximation on the sum rate is provided for the proposed family of metrics, which is validated through simulations. For a given number of active users and average SNR conditions, the base station is able to update certain transmission parameters in order to maximize the sum-rate function. On the other hand, the proposed sum-rate function provides a means of simple comparison between transmission schemes and scalar feedback techniques. Particularly, the sum rate of SDMA and time division multiple access (TDMA) is compared in the following extreme regimes: large number of users, high SNR, and low SNR. Simulations are provided to illustrate the performance of various scalar feedback techniques based on the proposed design framework.