Design of a high precision bandgap voltage reference

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.

Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.

A new 1-V high precision second-order compensated bandgap voltage reference (BGR) is presented in this paper. It utilizes a conventional first-order current-mode BGR to balance the Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT with a Proportional to Absolute Temperature (PTAT) voltage. The residual second-order error is corrected by the difference of two CTAT voltages with different non-linear terms through control of the collector currents of BJTs. All the circuits are designed using a standard 0.18μm CMOS process. The post-simulation results show that the maximum temperature coefficient (TC) of the proposed BGR at 1 V power supply is 2.5 ppm/°C over temperature range of −40 °C to 125 °C. The line regulation is 0.23 mV/V over supply range of 0.9 V–2 V. The low frequency power supply rejection of the circuit is −53 dB at 1 V power supply.

A high precision band-gap reference (BGR) with piecewise-linear compensation is designed in this paper. A low voltage Brokaw BGR architecture is employed to provide low output voltage. A high gain, low power supply rejection ratio (PSRR) operational amplifier is designed to improve the PSRR of the band-gap reference. In order to achieve temperature stability significantly lower than the traditional band-gap reference, a circuit which produces a current with positive temperature coefficient (TC) at high temperatures and 0 current at lower temperatures is designed. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. It's clear from simulation result that the TC of the output reference voltage approaches 2.61ppm/K over the military temperature range, the PSRR reaches 107.2dB at low frequency (f=0.1HZ), the whole BGR dissipates 0.4mW. In addition, the output reference voltage changes only 8.6μV when the power supply changes from 1.5V to 2.1V, that is to say, the power regulation ratio is 0.014mV/V.

This paper presents a high wide band power supply rejection ratio (PSRR) current mode bandgap reference (BGR) with a fast startup performance. The BGR includes three main enhancement techniques to improve the PSRR. The proposed design is implemented in 130nm CMOS technology. It only consumes 50μA from a 1.8V supply. The BGR provides 850mV reference voltage and has a power supply rejection ratio (PSRR) of 130dB from DC to 100Hz and more than 110dB till 100MHz. The temperature coefficient (TC) is 10 ppm/°C from -40°C to 125° C. The Bandgap start-up time is 70ns.

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.

SummaryVoltage references are typically designed by combining a complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltage references. However, in contrast to conventional voltage references, the proposed circuit generates a voltage reference by subtracting two PTAT voltages, resulting in an extremely low process‐dependent voltage reference. A novel subtractor is also proposed for subtracting PTAT voltages, which is used to generate the reference voltage. The temperature coefficient of the proposed voltage reference is further improved using a novel PTAT slope compensation technique. The proposed voltage reference is a MOS‐only ultra‐low power circuit that works with sub‐bandgap supply voltage. Simulation results using UMC 0.18 m technology MOSFETs show that the proposed circuit has a line sensitivity of 0.5%/V, a temperature coefficient of 21.37 ppm/° C, a power consumption of 15.6 nW, and an output voltage variation of only 0.22% due to process variations.

Based on the 0.18‐μm BCD process, this paper proposes a novel high‐order bandgap reference. Building on the original concave‐curve bandgap reference, high‐order compensation for the concave‐curve voltage‐mode bandgap reference is realized through β compensation and a piecewise compensation mechanism for source/sink currents. Under a 5‐V supply voltage and an ambient temperature range of −40°C to 125°C, the reference voltage is 1.205 V. The best temperature drift coefficient can reach as low as 0.875 ppm/°C, the power supply rejection ratio is 64.11 dB, the phase margin is 65.6°, the bandwidth can reach 6.2 MHz, and the total power consumption is 60.2 μA. With a power‐on time of 10 μs, the start‐up time of the bandgap reference is only 6.4 μs.

A −184 dB PSRR and 2.47 [formula omitted] noise self biased bandgap reference based on FVF structure

Electromagnetic Interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant NMOS-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Post-layout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/°C, for the temperature range from −55 to 125 °C. An EMI source of 4 dBm (1 V pp ) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum dc shift and Peak-to-peak ripple of −0.17 % and 822 μV pp , respectively.

A novel high-order curvature-compensated CMOS bandgap voltage reference (BGR) is proposed in CSMC 0.5μm CMOS process. By adding a piecewise-curvature current in the low temperature region and a piecewise-curvature current in the high temperature region to a conventional BGR, the proposed high-order curvature-compensated BGR achieves a reference voltage with lower temperature coefficient (TC). Simulation results show that the TC of the proposed high-order curvature-compensated BGR is only 0.62ppm/°C while the TC of the conventional BGR is about 2.82ppm/°C. The proposed high-order curvature-compensated BGR achieves the power supply rejection ratio (PSRR) of −53.98dB, −53.97dB, −52.84dB, −39.097dB and −21.75dB at 10Hz, 1kHz, 10kHz, 100kHz and 1MHz respectively.

The reference voltage is a core part of RFID tags, its performance directly determines the whole chip's life and performance. The temperature coefficient is one of the important performances of the reference voltage source and the high-order temperature compensation is an effective method to reduce the temperature coefficient of the reference source. A low temperature coefficient bandgap reference is designed based on the standard 65nm CMOS process, and the low-supply voltage operation with bandgap reference circuit with current mode structure. The designed CMOS bandgap voltage reference is in the range of -20°C to 100°C with temperature coefficient of 9.6 ppm/°C and provides a good Power Supply Rejection Ratio(PSRR) of 79dB in the low frequency. The results of simulation show that the design improve the performance of the bandgap reference voltage source effectively.

In this paper, A precision bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low-temperature coefficient (TC) is designed. It comprises a bandgap reference core circuit, a negative feedback loop, a nonlinear temperature compensation circuit, and a bias circuit. The bias circuit is used to increase the PSRR, a negative feedback loop is introduced to maintain the constant output reference voltage, and a nonlinear compensation circuit is used to increase the temperature drift coefficient of the bandgap reference. The voltage supply is 3. 3V. This simulation is based on the SMIC 0.1S$\mu$m CMOS process. The results show that the temperature drift coefficient of the bandgap reference source is 3.255ppm/°C in the temperature range of −40°C~130°C. The PSRR is 103. 192dB at the frequency of 1Hz. The power consumption is 13.1996$\mu$W. The offset voltage is 2.15591mV by Monte Carlo simulation.

With the recent advancements in ultra-low power wireless devices such as wireless sensor networks, the demand for nanowatt voltage references capable of operating below 1-V becomes a necessity. But due to the low voltage overhead imposed by the supply, most of the recent literatures on sub-1-V voltage references exhibited low power supply rejection ratio (PSRR) and thus were prone to switching noise induced at the supply line. This paper presents a high PSRR, subthreshold MOSFET-only voltage reference which has been simulated in $0.18 \mu\mathrm{m}$ TSMC CMOS process using the Synopsys HSPICE tool. The circuit employed a PSRR enhancement block that suppresses the variation along the supply of the core voltage reference. This circuit block implemented a negative feedback network that regulated the internal supply voltage of the core reference circuit. Simulation results showed that the proposed overall circuit generated an output voltage of 244.5 mV which operated properly at a supply voltage of 0.95-V and achieved a PSRR of −140.6 dB, −101.1 dB, − 64.3 dB, and −38.4 dB at 100 Hz, 1 kHz, 10 kHz, and 10 MHz respectively. The circuit also achieved a temperature coefficient of 9.9 ppm/oC from −25 °C to 100 °C while consuming only 74.6 nW. From these results, the designed high PSRR voltage reference provides the necessary specifications suitable for wireless sensor network nodes.

A novel 79-nW CMOS-only subthreshold voltage reference with 328-mV output voltage, which works down to 0.8-V supply voltage, is presented in this brief. In order to reduce the area and power consumption, the proposed circuit avoids the use of resistors and bipolar transistors. A current subtracting technique is proposed to realize the temperature compensation of reference current. Instead of the op-amp in traditional circuits, some cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). A novel structure consisting of a 1.8-V MOS transistor and a 3.3-V MOS transistor is utilized to accomplish the voltage temperature compensation and to further reduce the power consumption of VREF generator. The proposed voltage reference was fabricated in 0.18- ${\mu }\text{m}$ CMOS process. The measured results show that the temperature coefficient of the output voltage is 33.8 ppm/°C in the range from 10 °C to 100 °C, the PSRR is −55 dB @ 100 Hz at 1.2-V power supply, and the line regulation is 0.21%/V in a supply voltage range of 0.8 to 3.4 V. What is more, the power dissipation is 79 nW, and the chip area is 0.01 mm2. It is suitable for low-power applications.