Design of a Three-Operand Binary Adder Using Parallel Prefix Architectures

The paper gives us, a brief account of the design of 2D - discrete wavelet transform (DWT) implemented in VLSI architecture using Verilog HDL which achieves high speed computation. The main motive behind the development of the architecture is on giving efficient hardware utilization along with high operating speed and less number of clock cycles. To verify the proposed scheme, 2D DWT is applied on a grey image of size 128*128 to get all the four components (average, diagonal, horizontal and vertical), this wavelet decomposition is verified and obtained in Xilinx 14.2 version software using Verilog HDL; circuit is planned, modelled (simulated) in Verilog HDL, and finally the result is validated in FPGA Spartan 6 to get the output 2D-DWT computed image back. This is a single chip implementation where discrete wavelet transform can be used in VLSI design more efficiently than other transform. It is depicted that the operation carried out with specified processing speed of the designed architecture based on the proposed scheme is good than those of the other architectures designed using other existing schemes, and it has less hardware utilization.

FPGA packages have maximum size constraints much larger than the number of IO pins. The resulting IO bottleneck during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. This cuts more critical timing paths between packages and drastically decreases the circuit operational frequency. In this paper, a bottom-up circuit partitioning method with cone structures is presented. The solution can minimize the delay of critical paths that slow down the circuit without changing the number of partitioned packages.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Chip-level clock tree synthesis (CCTS) is a key problem that arises in complex system-on-a-chip designs. A key requirement of CCTS is to balance the clock-trees belonging to different IPs such that the entire tree has a small skew across all process corners. Achieving this is difficult because the clock trees in different IPs might be vastly different in terms of their clock structures and cell/interconnect delays. The chip-level clock tree is expected to compensate for these differences and achieve good skews across all corners. Also, CCTS is expected to reduce clock divergence between IPs that have critical timing paths between them. Reducing clock divergence reduces the maximum possible clock skew in the critical paths between the IPs and thus improves yield. This paper proposes effective CCTS algorithms to simultaneously reduce multicorner skew and clock divergence. Experimental results on several test-cases indicate that our methods achieve 30% reduction in the clock divergence with significantly improved multicorner skew variance, at the cost of 2% increase in buffer area and 1% increase in wirelength.

A new field programmable gate array (FPGA) design algorithm, Maple-opt, is proposed for technology mapping, placement, and global routing subject to a given upper bound of critical signal path delay. The basic procedure of Maple-opt is viewed as top-down hierarchical bipartition of a layout region. In each bipartitioning step, technology mapping onto logic blocks of FPGAs, their placement, and global routing are determined simultaneously, which leads to a more congestion-balanced layout for routing. In addition, Maple-opt is capable of estimating a lower bound of the delay for a constrained path and of extracting critical paths based on the difference between the lower bounds and given constraint values in each bipartitioning step. Two delay-reduction procedures for the critical paths are applied; routing delay reduction and logic-block delay reduction. The routing delay reduction is done by assigning each constrained path to a single subregion when bipartitioning a region. The logic-block delay reduction is done by mapping each constrained path onto a smaller number of logic blocks. Experimental results for benchmark circuits demonstrate that Maple-opt reduces the maximum number of tracks per channel by a maximum of 38% compared with existing algorithms while satisfying almost all the path delay constraints.

Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For digital signal processing (DSP) hardware, variations in circuit parameters can significantly affect the quality of service (QoS). Existing post-silicon calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, frequency, or body bias and typically incur large delay or power overhead. This paper presents a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least significant bits. Hence, truncation of these bits, by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. The proposed technique is applied to two common DSP blocks, namely discrete cosine transform (DCT) and finite impulse response (FIR) filter. Simulation results show significant reduction in critical path delay along with a graceful degradation in the QoS. They also show large improvement in manufacturing yield (41.6%) with up to 5X savings in power compared to existing approaches such as voltage scaling and body biasing.

In this paper the timing of an existing placement is improved by netlist modification. Placement timing is defined as the maximum delay along the most critical path plus the maximum clock skew. Post-placement buffer reoptimization balances clock buffer trees to minimize clock skew and speeds up critical path delays to minimize chip timing. Initial results show upto a 55% reduction in critical path timing with only a 5% increase in area. >

A static timing verifier is an important tool in the design of a complex high performance VLSI chip such as an Alpha CPU. A timing verifier uses a simple and pessimistic delay model to identify critical failing paths in the design, which then need to be fixed. However, the pessimistic delay model results in a large number of correct paths being identified as failing paths, possibly leading to wasted design resources. Therefore, each critical path identified by the timing verifier needs to be analyzed using a circuit simulator such as SPICE in order to confirm that it is a real failure. Setting up such a simulation is complex, especially when the critical path consists of structures appearing in a datapath of the CPU. In this paper, we present algorithms for the construction of a model for simulating the maximum delay through a critical path. This technique has been used to analyze several critical paths during the design of a 300 MHz Alpha CPU.

Recent technology advancements have put a lot of emphasis on the optimization of three main aspects - speed, power, and area. The speed of a digital circuit is always dependent upon clock frequency. The clock frequency of a digital circuit is predominantly influenced by the computational cost of the critical path. The critical path of the digital circuits that contain combinational and sequential elements like FIR, IIR Filters, Multipliers, Adders, Digital Signal Processors (DSPs), etc. can be optimized by rearranging the delay(s) of the critical path, which eventually reduces computational cost without trading with the functionality and input-output relation of the circuit. The term ‘Retiming’ is used to describe the technique of reorganizing the storage elements (registers) in a digital circuit while maintaining its functionality. Currently, python is becoming a choice for a large community of software developers, in the VLSI domain also it is gaining popularity as a scripting language. In this article, the python implementation of the retiming technique is proposed, which takes a Data Flow Graph (DFG) of a non-retimed Digital Circuit as an input to generate the optimized DFG with less critical path delay by Brute Force search, thereby improving overall performance.

To achieve strong data protection across diverse applications, a polymorphic version of the Advanced Encryption Standard (AES), named P-AES, has been introduced and executed. In P-AES, the main operational parameters are altered dynamically with each new encryption key, and these values are accessible only to authorized users during execution. To facilitate this polymorphic feature, the standard AES processes— Substitute bytes, Shift rows and Mix Columns—have been adjusted to depend on the key. Consequently, the internal operations are uniquely tailored for each encryption key, while the recipient can extract the transformation logic directly from the key, ensuring secure compatibility. The entire P-AES design has been articulated using Verilog HDL and implemented on an Artix-7 FPGA with Xilinx Vivado 24.1 for synthesis and simulation. In line with Kerckhoffs’s principle, P-AES depends solely on the confidentiality of the encryption key, not the algorithm itself. The design accommodates 128 distinct operational modes, complicating potential attacks. Key and plaintext avalanche scores were 0.521 and 0.504, respectively. These enhancements, validated through avalanche testing and HDL implementation, indicate that P-AES is a promising solution for high-speed and secure data encryption in contemporary systems.

Dealing with timing failures in nanometer-scale ICs requires a deeper understanding of critical timing paths, noise mechanisms, process variability, timing rules, and the statistical interaction of random parameter values and distributions. This article examines the factors that affect nanometer timing at both the component and system level. It reviews the timing properties of nanoscale logic gates, latches, edge-triggered flip-flops, clocks and their interconnects, resistive vias, and pipeline structures. It also discusses the challenges involved in determining critical timing paths and the underlying causes of nanometer timing failures.

The detection of speed-related defects relies on fault excitation and propagation along critical speed paths in the design. Different types of structural tests detect speed paths differently. In this paper, we compare the capabilities of speed path detection using Ndetect and timing-aware transition tests on silicon. Experimental data on the latest quad-core AMD Opteron™ processor is collected. Results show either pattern set catches a significant amount of speed paths that is not predicted as critical timing paths. This illustrates the difficulty in pre-determine a subset of critical timing faults targeted for timing-aware transition test, while shows Ndetect transition test can be a practical solution for general speed path profiling.

Activity-aware prediction of Critical Paths Aging in FDSOI technologies

Addition is a timing critical operation in today's floating point units. In order to develop faster processing, an end-around carry (EAC) was proposed as a part of fused-multiply-add unit which performs multiplication followed by addition [5]. The proposed EAC adder was also investigated through other prefix adders in FPGA technology as a complete adder [6]. In this thesis, we propose a 128-bit standalone adder with parallel prefix end around carry logic and conditional sum blocks to improve the critical path delay and provide flexibility to design with different adder architectures. In previous works, CLA logic was used for EAC logic. Using a modified structure of a parallel prefix 2n-1 adder provides flexibility to the design and decreases the length of the carry path. After the architecture is tested and verified, critical path is analyzed using FreePDK45nm library. Full custom design techniques are applied carefully during critical path optimization. Critical path analysis provides fast comparison of the total delay among different architectures without designing the whole circuit and a simpler approach to size the transistors for lowest delay possible. As a final step, datapath is designed as a recurring bitslice for fast layout entry. The results show that the proposed adder shows 142ps delay, 2.42mW average power dissipation, and 3,132 sq. micron area assuming there is not much routing area overhead in the estimated area.

This paper presents the design of multi-cycle 32-bit Reduced Instruction Set Computer (RISC) processor for better performance and higher speed of operation. The processor is capable of executing more number of instructions with simple design and less critical path delay. The designed processor was simulated and synthesized using Xilinx 14.7 ISE design suite. The processor executes each and every instruction in more than one cycle that's why the term multi-cycle. Each instruction is divided into three main states namely the Fetch state, the Decode state and the Execution state. The first two sates remain the same for all the instruction the last state, however depends on the type of operation performed in that instruction.

Circuit designers and high-level synthesis tools have traditionally used circuit hierarchy to partition circuits into packages. However hierarchical partitioning can not be easily performed if hierarchical blocks have too large a size or too many I-Os. This problem becomes more frequent with field-programmable gate arrays (FPGAs) which commonly have small size limits and up to ten times smaller I-O pin limits. An I-O bottleneck often occurs which during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. More critical timing paths between packages are cut and circuit operational frequencies are drastically reduced. In this paper, two new partitioning algorithms are presented that use cone structures to partition large hierarchical blocks into FPGA's. Cone structures are minimum cut partitioning structures for netlists with low fanout, and clustering structures for partitioning netlists with high fanout. Cone structures also allow for full containment of critical paths. When used with good merging and cutting strategies, results show the cone partitioning algorithms given here produces fewer FPGG partitions than min-cut with good performance.