Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

ABSTRACTQuantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

In today’s electrical or electronic designing, power dissipation becomes dominant. The promising alternative to these technologies is the reversible computing. Because for irreversible circuits, information is lost and it dissipates energy as heat. The dissipated energy is proportional to the number of bits lost during computation. In case of reversible circuits, they do not dissipate energy in a large amount as irreversible circuits. So information is not lost in reversible circuits during the execution of operation. Thus generation of unique outputs from the particular inputs and reconstruction of inputs from the particular outputs can be achievable. So in the view point of designing issues, reversible logic is a promising field of research that finds applications in low power computing, quantum computing, optical computing and other emerging computing technologies, bioinformatics and nanotechnology-based systems. Here, an approach for the designing of optimized reversible parallel multiplier (ORPM) by reversible gates has been followed. In this regard, this paper represents a new partial reversible gate RPPG for partial product generation for the designing of ORPM. Also, two designing methods are proposed to design ORPM and a comparison is also made between these two methods and the existing reversible multiplier circuits reported in the literature in perspective of the number of reversible gates, constant input, garbage output and total logical calculation.KeywordsReversible logicReversible gateReversible parallel multiplierGarbage outputConstant inputs

Reversible logic preserves information and provides low power computing. Floating point multiplier is an important part of arithmetic in DSP applications. IEEE754 provide two basic and widely used formats for representing floating point numbers namely Single Precision Floating point (SPFP) and Double Precision Floating Point (DPFP). In this paper, we have proposed designs for Reversible SPFP and DPFP point multiplier which requires optimum design of 24X24 and 53X53 multiplying circuitry with reversible gates respectively. Also we presented sign bit calculation and exponent bit calculation circuits by reversible logic. Reversible Mantissa bits calculation circuitry requires consumes more area as it has large value of quantum cost and garbage outputs as compare to reversible sign bit and exponent bits calculation circuitry. So, we mainly focused our work on to minimize the area consumed by the reversible mantissa bits calculation circuit by minimizing the value of quantum cost and garbage outputs of it. In this paper, we presented two ways for partial products generation with reversible gates. We propose a new design of reversible 12X12 reversible Wallace tree multiplier for single precision and double precision mantissa multiplier circuit. Also 5X5 and 5X12 reversible Wallace tree multiplier for double precision multiplier. Here we use the optimized designs of reversible half adder, Full adder and 4:2 compressors. In the final summation stage, we carefully shifted the product terms and add them. For this stage we have carefully chosen the adders and compressor in such way to get the optimized results in terms of quantum cost and Garbage output. We have also shown the improvement in single precision floating point multiplier in terms of Quantum cost and Garbage output.

In the midst of emerging technology, reversible computing is promising due to its application in the field of quantum computing. The computing hardware plays a significant role in digital signal processing DSP and multimedia application; one such major computing hardware is multiplier. It is a practice to choose multiplier to compute square of an operand. Multiplication hardware requires more elementary computations which leads to performance degradation in terms of reversible performance metrics like quantum cost, garbage outputs, and ancilla inputs. Ancilla inputs and garbage outputs are overhead bits in a reversible circuit. Reversible quantum computers of many qubits are extremely difficult to realize, thus we propose garbageless circuit design for reversible square computation. The proposed design methodology is based on recursion. Recursion technique is adapted from Karatsuba's recursive method to compute square of an operand; we designed inverse computation units to retrieve the inputs and obtain garbageless circuit. On comparing proposed circuit design with existing reversible square designs and Karatsuba multiplier design, we observed that our work improves number of input lines which includes data lines and ancilla lines.

Reversible logic is a new rapidly developed research field in recent years, which has been receiving much attention for calculating with minimizing the energy consumption. This paper constructs a 4×4 new reversible gate called ZRQ gate to build quantum adder and subtraction. Meanwhile, a novel 1-bit reversible comparator by using the proposed ZRQC module on the basis of ZRQ gate is proposed as the minimum number of reversible gates and quantum costs. In addition, this paper presents a novel 4-bit reversible comparator based on the 1-bit reversible comparator. One of the vital important for optimizing reversible logic is to design reversible logic circuits with the minimum number of parameters. The proposed reversible comparators in this paper can obtain superiority in terms of the number of reversible gates, input constants, garbage outputs, unit delays and quantum costs compared with the existed circuits. Finally, MATLAB simulation software is used to test and verify the correctness of the proposed 4-bit reversible comparator.

Reversible computing is one of the most promising technologies in the design of low‐power digital circuits, optical information processing, quantum computing, DNA computing, digital signal processing, and nanotechnology. The main purpose of the design of reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. A gate/block is reversible if the number of inputs and the number of outputs are equal and there is one‐to‐one correspondence between them. Latches are considered as one of the most important digital structures that are widely used as building blocks in the design of sequential circuits. Here, eight new reversible blocks are first offered. Then using some of them, several effective designs of reversible D, T, and J‐K latches are proposed. The results of the evaluations indicate that the proposed latches are superior in terms of quantum cost (QC) than previous designs. Moreover, they are very close to or better than the best previous designs in terms of criteria such as gate count (GC), constant inputs (CI), and garbage outputs (GO).

Quantum Cellular Automata (QCA) is an emerging technology in the current nano-technical world where electrons are used in the quantum cells for information storing and transmitting. The analytical and numerical design of different types of combinational and sequential circuits with the help of QCA spin technology is now under process. In this paper, the design of a multilayer 3D Reversible “Full Adder-Subtractor” by using Quantum Cellular Spin Technology (‘QCST’) is explored under the consideration of different trade-offs. The trust area of this paper is to reduce the cell-complexity, occupied unit-area, and clock-zone (latency of the design). The dissipated power also calculated under the presence of multilayer wire crossing with reversible logic. In this proposed structure reversible 3 × 3 “Feynman Gate” is used and the garbage outputs are utilized to design carry out and borrow out in the proposed design. The 3 × 3 “Modified QR Gate” (Reversible gate also) is also used to provide a new extra logical expression that is used for super-computing. In this also cited the logical design and validate by Verilog Code using Xilinx.

The semiconductor industry has been experiencing a massive upgradation in terms of speed and device performance due to device scaling since the invention of MOSFETs in 1960s, but simultaneously power dissipation has also been a major concern. With the device scaling having reached its limit, researchers are looking for a breakthrough technology. One of the emerging fields in the VLSI industry is Reversible Computing. This technology has largely attracted the researchers, because of zero power dissipation in reversible logic circuits. The proposed work here is towards designing an ALU using reversible quantum gates, which operate on qubits. The proposed ALU performs both arithmetic and logical operations, either of which can be selected as per the requirement and additionally, it is capable of detecting single bit error. The design uses Fredkin and CNOT gate, which are parity preserving reversible gates. The proposed design is modelled using Verilog HDL and simulated in Modelsim software. The design is focused on reducing the number of gates, quantum cost, Garbage outputs and ancillary inputs or constant inputs.

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

A new design for XOR gate-based reversible double Feynman gate in nano-scale quantum-dots

Low power consumption is a vital issue for digital circuits in today's technological era. Hence reversible logic plays a significant role in designing low power digital circuits. In the existing literature, a lot of research has been done on reversible sequential circuits. In this paper author presents the design of asynchronous and synchronous digital counters using a novel reversible gate. This design intends to optimize the counter in terms of number of reversible gates, delay and garbage outputs and thus complexity of the circuit reduces. Hence this optimized design will significantly strengthen the performance of the sequential counters concerning size and power utilization.

Reversible logic is an emerging research area. Its ability to reduce the power dissipation has made these circuits lossless circuits. Irreversible circuits or classical circuits have energy dissipation is proportional to the number of bits lost during computation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. It has application in diverse fields such as low power CMOS design, optical information processing, cryptography, quantum computation and nanotechnology. This paper proposes a reversible design of Flip Flops, Counters and Universal shift register. Universal shift register is an important memory element of the sequential circuit family. In this paper we proposed efficient design of reversible universal shift register that is optimized in terms of quantum cost, delay, garbage outputs. Each module has been coded using Verilog then simulated using Modelsim and prototyped in Xilinx-Spartan 3.